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Recent content by Abhi.ranjan

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    Post layout and routing Cadence innovus verification

    Which tool in Cadence should be used for 1. GDS vs gate-level netlist. 2. Gate - level vs RTL
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    Post layout and routing Cadence innovus verification

    How do we verify the functionality of the gds file created by innovus ? Or which tool we use to verify it?
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    Tap wells in Cadence innovus

    Sorry to bother you more, can you please suggest something for Cadence 180nm in innovus flow.
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    Tap wells in Cadence innovus

    Thankyou for replying! So, how to place the cell, how will it understand that cells will be placed at the tap. I mean what pattern to be used or where exactly to place.
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    Tap wells in Cadence innovus

    How do we place tap wells in Cadence innovus so that it adjusts automatically according to the standard cells and don't throw any error?
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    RTL to GDSII stream in issue

    While streaming in the gds file (generated by innovus), I am not able to see all the layers even the metal connection are missing only the drawing of outline are present. What can be the issue?
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    [SOLVED] I am getting an error during post synthesis while running Cadence Innovus. Can anyone help me to resolve it?

    Hi ThisIsNotSam I figured out the correct technology and macro files and now I am not deleting metal 6 layer. Thankyou for your insights.
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    [SOLVED] I am getting an error during post synthesis while running Cadence Innovus. Can anyone help me to resolve it?

    Actually I created a copy of it and then edited it. Also I am not able to get the technology file and macro file of same IP. That's why I tried that approach. Can you help me with the files?
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    [SOLVED] I am getting an error during post synthesis while running Cadence Innovus. Can anyone help me to resolve it?

    Thankyou for the reply I will try it. Although it's working correctly with deleting the metal 6 from lef file.
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    [SOLVED] I am getting an error during post synthesis while running Cadence Innovus. Can anyone help me to resolve it?

    I have access to Cadence with help of my college. The files we are using is . 1. header5_V55.lef 2. fsa0m_a_generic_core.lef 3. FSAOM_A_GENERIC_CORE_ANT V55.lef 4. foaDa_o_t33_generic_cd_jo.lef 5. FOA0A_O_T33_GENERIC_CD_IO_ANT_V55.lef Thankyou
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    [SOLVED] I am getting an error during post synthesis while running Cadence Innovus. Can anyone help me to resolve it?

    What are we doing? - we are trying to design an ALU. (From LVS to gds) Where do these files come from? - These lef files are taken from UMC_180nm_Sansh Pdk ( from io as well as std cells) And the last answer ... We are working with an academic technology. Thankyou
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    [SOLVED] I am getting an error during post synthesis while running Cadence Innovus. Can anyone help me to resolve it?

    Hii, Thankyou for the response. Can you let me know about all the 5 suspicious things. Also I deleted the metal6 layer in my .lef file and I was able to run the Innovus and get some output. Is it correct way to do? Also how can we generate .io file using Innovus? Thankyou

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