Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi everybody.
im new here and i hope i can get help
my problem is how to prove that the best P/N ratio for minimum avearge delay is √(µ)
i proved that for inverter but i cant for NOR2 or NAND2 any help pleas showing solution stips
thank you
ps: what section in this forum for vlsi
:-(:-(:!:
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.