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Updates:
I used the circuit provided in Figure 4 of https://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf to test the chance of getting metastable with the implemented design and no luck. I now suspect that I don't have delay through those blocks.
In the fpga editor, the...
So if it's kept if I do this trick, but it's screaming *no load* if I leave it as it is, should that tell me that the signal is somehow unconnected to where it should be?
Does having no load mean the same thing as not driving a signal?
So I get no more errors if control_data_coarse & control_clk_coarse are declared as outputs in the top_module instead of wires. The initial warnings being
I don't understand how declaring that as an output would give it a load. Can anyone explain?
Thanks for the answers, mrflibble!
I've did some of the code trimming last night and also the named port connections. Didn't quite got to the problem, as I still have no loads on those signals, even with as few as 3 wires per signal. I'm still missing something, I'm sure of it.
But I have some...
Indeed, with those constraints on the LUTs, the lower bit of each of the two vectors gets a load.
Which is odd because, basically, control_clk_coarse and control_clk_fine are generated in the same manner, only for different values of the input in the case switch.
Also, the output of those...
Thanks for the quick reply, mrflibble !
This is the paper from where I got the idea -
https://people.csail.mit.edu/devadas/pubs/ches-fpga-random.pdf
And I caught the idea that I need to keep XST from optimizing what I did, while doing research for the project. The thing is, I'm unsure as to...
Well, the whole design intends to be a random number generator based on metastability (asynchronous perversions in fpga design?). It is not my work, not claiming anything, I'm just trying to implement an idea of someone way smarter than me.
So, the short version. I 'm working with a Spartan 3E...
So <p/GLOBAL_LOGIC1> is the "control" input..
The big picture is to make a programmable delay line. The control input would influence the path inside the LUT giving me the fine delay difference I'm looking for. So.. it *should* drive/influence the output, although not by value.
The above example...
Hi,
I'm trying to use a LUT4_L primitive on a Spartan 3E.
top module :
module top_model(
input clk,
input reset,
output out
);
coarse_pdl p(clk,reset,out);
endmodule
coarse pdl :
module coarse_pdl(
input in,
input control,
output out
);
LUT4_L #(
.INIT(16'h5555) //...
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