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Recent content by aaronhor

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    Future of analog design

    Analog will never goes die. New application coming in which require fast speed and high bandwidth can only be satisfied with analog circuits. But I do believe analog designer in the future might need to involve in digital design as well as the system getting more and more digital. **broken link...
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    Could somebody explain Analog IC Design Flow?

    There is a equilvalent HDL entry in analog design, which is verilog-A. It can be used in spectre simulator to model analog blocks such as op-amp, comparator, etc. The detail analog design flow can be found at : **broken link removed**
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    help:books addressing device physics on EDA

    I think "semiconductor physics and devices " by Neamen is very a very good reference. Analog Circuit Design Textbooks | Circuit Design World
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    Beginner - Layout techniques

    I think razavi book has covered a good portion on introduction to layout. "The art of analog layout" by Alan Hasting is of course all time favourite Analog Circuit Design Textbooks | Circuit Design World
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    CMOS operational amplifier needed !!!

    Many textbooks have covered this. Examples include textbooks by razavi, k.Martin, P.Allen, etc. Analog Circuit Design Textbooks | Circuit Design World
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    Beginner in analog circuit design

    I always find razavi book easy to follow. It is a good textbok to start with. Analog Circuit Design Textbooks | Circuit Design World
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    suggest a good book for analog electronics

    I think Razavi and Willy sansen books are good to start with. Analog Circuit Design Textbooks | Circuit Design World
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    Who is your idole in Analog Design?

    I like willy sansen and Behzad Razavi. Analog Circuit Design Textbooks | Circuit Design World
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    want to know how to convert verilog netlist to spice netlist

    you can use v2lvs command . More details can be found on the link: How to convert Verilog code to Spice format | Circuit Design World
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    smart spice netlist to schematic ?

    We can create a schematic from a spice netlist. In the CIW windows, go to File -> Import -> SPice. Fill up the input, oputput and devicemap file sections. As explained in more detail in the following website. How to create a schematic from spice netlist | Circuit Design World
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    What is a layer map file and when do we need it?

    there is another link on this layer map issue. How to write an output-map file | Circuit Design World
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    Question of import gds from encounter using Virtuoso.

    I believe you have used the wrong map file? So they are mapped to the wrong layers in virtuoso. You may refer to this site for further details on how to import GDS file from SOC encounter to Virutuoso. How to stream-in gds file from SOC encounter to Virtuoso | Circuit Design World
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    Encounter - export layout to Cadence Virtuoso

    I think you are using the wrong map file. The flow is basically correct. You can go through the steps descibed in this site: How to stream-in gds file from SOC encounter to Virtuoso | Circuit Design World
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    File extension: Spice Netlist and Spectre Netlist in Cadence

    The flow is perfectly correct. I have found a similar flow in another link, and follow through it successfully. How to include a spice netlist and simulate it in spectre environment | Circuit Design World
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    how to do mixed signal simulation in spectre using netlist?

    It is indeed possible to use spice netlist generated from verilog code and simulate it together with analog blocks. You can create a symbol to represent the spice netlist, modify the CDF parameters, and include the digital cell spice netlist in the model library. Then you can run the simulation...
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