Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by aamalathithan

  1. A

    Technology Library needed

    Hi, I am looking for a latest synopsys technology library. My school has the following and i think they are very old. Design Compiler throws a error that trip-point thresholds are not mentioned. lsi_9k.db lsi_7k.db lsi_lsc15.db Thank You.
  2. A

    Primetime Environment setup

    Hi , i fixed that first error and reads the file lsi_10k successfully. But it still says that the library lsi_10k does not have a complete set of trip-point thresholds.
  3. A

    Primetime Environment setup

    Hi , I am trying to read a synthesized netlist into prime time, but it throws the following errors. Errors have been highlighted in RED in the console output section Did anyone run into these kind of errors ? Kindly looking for help. My Script: set link_library lsi_10k.db set...
  4. A

    Writing values into memory and reading those values. Timing Issue!!!

    Anyone can help me with this ? Still couldn't fix it !!!
  5. A

    TCL Regular Expression

    Yeah. I was very confused with it. I found it in the list of Tcl Interview questions.
  6. A

    TCL Regular Expression

    Hi, Can anyone help me to confirm what the following expression matches to ? (. * ? +)
  7. A

    [SOLVED] using randomize function in vcs

    Hi, i am trying to randomly generate values in system verilog using "randomize" function. But, the simulator VCS throws me the following error: Error-[IND] Identifier not declared mem_test.sv, 31 Identifier 'randomize' has not been declared yet. If this error is not expected, please...
  8. A

    Highlighting Syntax for System Verilog files in VIM (GVIM)

    Hi, My Vim editor does not highlight syntax for Sytem Verilog files. I want to know how to make it work for both vim and gvim for system verilog files. Thank You.
  9. A

    Writing values into memory and reading those values. Timing Issue!!!

    Hi, I am trying to design a memory (logic [7:0] memory [0:31]) in system verilog. First I write 0s into all the address of my memory, then I read one by one. After writing 0 into the address memory[31], i start reading from memory[0]. But i am getting x. I think there is some race...
See more

Part and Inventory Search

Back
Top