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Recent content by a991852

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    [MOVED] DAC area saving topologies, and noise

    Hi All, I'm trying to make a DAC with less area using MiM Capacitors Basically Split DAC uses less area than a binary weighted capacitors since for a 6 bit split DAC, only area of 2 3-bit DAC are required, drastically reducing area. Split DAC (6-bit DAC): 1C 1C 2C 4C 1C 2C 4C Binary...
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    Split Capacitor DAC, how to layout the split capacitor Cs?

    Thats a great idea too! Thanks!
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    Split Capacitor DAC, how to layout the split capacitor Cs?

    Hi All, I'm trying to implement a split capacitor array DAC, which is shown in this following picture: The problem is that the scaling capacitor is not a unit sized capacitor, which cannot be placed inside the capacitor array. My Idea for the solution is that: If the scaling capacitor is...
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    DAC using MiMCap, How to reduce parasitic capacitence

    Thanks for your reply! To Xingkongwu, can you explain to me what is a sub_DAC? Or any information I might be able to find? I tried to search for sub DAC on google, but it didn't say much.
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    DAC using MiMCap, How to reduce parasitic capacitence

    Hi, thanks for your reply! This is the GDS file, technology is TSMC 180nm
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    DAC using MiMCap, How to reduce parasitic capacitence

    Thanks for your reply! To Keith1200rs, There are 1 (bit 1) 2 (bit 2) 4 (bit 3) 8 (bit 4) 16 (bit 5) 32 (bit 6) 64 (bit 7) 128 (bit 8) 256 (bit 9) 512 (bit 10) 1024 (bit 11) 2048 (bit 12) Capacitors. I think I can try larger capacitance are try to put extra metals (connections) to balance the...
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    DAC using MiMCap, How to reduce parasitic capacitence

    Thank you guys for your replys! To tgootee, what I am doing is the a common-centroid layout, the unit capacitance are layed-out with a specific pattern. The reason why I cannot use parasitics as a part of the circuit is that the largest bit, for example 12, has at least 50% of the parasitic...
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    DAC using MiMCap, How to reduce parasitic capacitence

    Hi All, I'm currently drawing a 12-bit DAC in TSMC 180nm Technology, and I'm using a 1f, 2f, 4f approach where the capacitances are doubled for every bit. This is my layout And this is one of the corners However, I'm getting this problem with large parasitic capacitances that are a...
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    How to use Auto Route Function for Allegro?

    I'm new to Allegro, and I basically threw in a few resistors to try to use the auto route function. The automatic router is setup without any constraints, and left all the options as-is. When I clicked Route, it will pop-up a progress window, and when it finishes, the resistors are left...
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