Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi everyone, I'm new to trying to hand-crank VHDL and I'm having a wee bit of a problem. I usually use auto-generated code so I'm not too used to writing it myself. The problem that I'm having is that the code is being generated with one-bit signals being defined as std_logic type but the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.