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In the docs i encountered the term WDM IF and SDH IF.
I couldn't find any meaning for the abbreviations. What does IF stand for in this case?
I have attached the graph where the usage is shown.
I 'd like to learn to make cryptographic projects involving
a great part of number theory , especially in assymetric cryptography.
Could anybody provide some examples in VHDL code or methodology
of implementing these things?
I don't quite understand the destinctions between
such design techniques as:
Loop Unrolling
Inner-Round Pipelining
Outer-Round Pipelining
Please explain me
Guys, tell me please in which case should I list all the signals in the process and
in which case not all of them?
After synthesis in XST I got number of bonded IOBs overused 133%. I don't
quite understand what can be the reason for this.
Guys, I've encountered a problem of creating and managing a RAM.
Could you please give an example of using a memory to store 256 bits
of data, for example, a key, and managing with write enable, clk signals.
Guys I can't solve the problem of writing VHDL code, that
implies executing an intialization part that is to be executed only once and
the other part is to be regularly repeated and both parts(init and work) have
the same signals.
How can I solve it?
Re: VHDL question
I used the if (Start='1') generate... statement but
the error message says:result of operator = is not static.
But Start cannot be static because it's a start pulse.
Is it possible to have a process inside another process?
I need to a certain component to be executed based on a
set condition, for example when the start pulse is excited.
What code should I use?
P.S. A component is a concurrent statement using "when" operator
When I run synthesis using Xilinx ISE's XST i get the warnings:
PACKER Warning: Lut gost_top_SM1out<1>lut driving carry gost_top_SM1out<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result...
I need to transfer the c++ code to make a VHDL program in
Xilinx ISE environment.Xilinx ISE doesn't support multidimension arrays. How can I adapt the code of the c++
program where a 2D array is used and many 32 cycles are required?
Are there any PROMs (one time programmable) that get activated
when the power is on and without th help of any microcontrollers
the data stored on the PROM is readout.
It's needed to pass a predefined sequence to a device.
Are there such Altera PROMs, what is the name of such a PROM?
I have a differential signal with dc offset 3.3 V.
The problem is to drive an optical VCSEL transmitter.
What can I do to convert the signal and make it suitable for optical transmision.
Can I use the high voltage wire and GND ignoring the low voltage wire
then pass through a threshold device...
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