Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
pipeline　dnl
I using a slow Ramping signal(ideal) to simulate the DNL of a 10bit pipeline ADC.
I found that there is non-monotonicity digital output code. In this cases, how can I plot the DNL curves and INL?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
