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@OP ... I'll share a story.
I once presented a design to some fellow(s) at a very large semiconductor company (by fellow a mean title). They asked me what channel lengths i used for DAC current mirrors, to which I replied, minimum. There was some consternation, as they said the process...
1) Missing phase on Cf to ground.
2) Please show simulation in/out gain, for empirical gain you received.
Cs size is usually set by SNR requirements of converter and hence kT/Cs. Higher Cs, better SNR. If you are just simulating for functionality, you can try something like 1pf.
For debugging...
It looks like the DC level is periodically refreshed to ground by a clock controlling the feedback path switch. DC gain would be -1, I think (inverting side is input).
The unity gain frequency will be a function of the internals of the op amp in conjunction with the load capacitance. Typically...
I don't understand where some of this is coming from. Could you either show a more clear derivation with equations or references/sources?
For example, LG=100 or 20dB. As far as I know, voltage gain is 20*log10(vo/vi) so 20*log10(100) =40dB not 20 that is likely power gain. And why are you...
Not sure how you calculated your accuracy,
but I would use the following.
You have Acl = 1.8/5e-3 = 360
So, B = 1/360 (feedback factor)
For Accuracy, we can use Acl_err ~ 1/(Ao*B)
so Ao >= 1/(Acl_err*B) >= 1/(.01/360) >= 36000 or 91dB
using 70dB Ao only gives gain 3162 or 11.4% error
If you...
Most of the intuition you are asking for does revolve around small signal modeling.
As a linear amplifier, the MOSTFET operates as a transconductance device (gm) so small signal voltage in gives small signal current out (iout=gm*vin). If you want to have a voltage out, you provide some load...
I think a lot of analog designers will struggle with gm/Id because programming isn't exactly their forte. You have to be able to develop tables to work with based on your process and tools that you are comfortable with, and then be able to set up the problems in a way that matches the tools and...
So i expect the Vgs>Vt threshhold voltage to move also ,because we need to put Vg=Vt+Id*Rs to get the transistor opened .
but as you can see in the simulation bellow it stayed steady.
Why is that?
Took me a minute to understand his notation (Vd = Va looks like 1/alpha etc...).
When you say bias...
Breifly,
1) Phase Margin. Increase. This type of architecture usually has a miller pole splitting capacitor between the two stages. Without it the dominant and non-dominant poles become close and give bad phase margin. Look up miller two stage OTA or Op Amp and using miller compensation cap to...
It wouldn't really benefit you much (especially fellow students) to get the answer for a try out if you have zero idea on how to do it and it's never been taught. I'm guessing he's feeling for how advanced some students might be. Best approach would be to look up Razavi books and gain and...
This is why I said you might have a huge number of parameters to sift through. Imagine you have a voffset with a granularity of 1uv and range of 50mv. That's 50,000 parameter points alone! Then you add in W,L etc... the search space grows large quickly. Like someone else pointed out, if...
Agree with jjx on the optimizers. They show a lot of promise, but there are a tremendous number of free design variables and hence permutations to have to sift through. On top of that setting up the optimization targets is not simple. This costs a lot of time to simulate which may or may not...
Although this is often the case (as in a simple diff pair here) , it's not always true in general otas. A simple example is a folded cascode architecture where M3,4 sources must provide more than Iss. A better general rule is simple that sum of the currents entering/leaving Iss drain should...
There are all kinds of training courses you can sign up for.
https://www.cadence.com/en_US/home/training/all-courses.html
Aside from that, I don't see much free literature out there. Most people I know learn cadence in school or on the job training.
You were not too clear about the specific section or equation you are asking.
I'll assume it is eq 8 p1216, you meant. In it, he explains the voffset(variance) is proportional to some weighting terms. One of which is ((gm2,3)/gm1)^2*var((deltaVT(2,3)). In order to bring this down, one can lower...
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