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About ranjithanih

Basic Information

Areas of Interest
Area of specialization:
ASIC Design, PLD, SPLD, GAL, CPLD, FPGA Design

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Total Posts
Total Posts
1
Posts Per Day
0.06
General Information
Last Activity
5th October 2017 11:14
Join Date
3rd October 2017
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Points
Points
17
Level
1
Points: 17, Level: 1
 
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33%
Points required
33

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0%
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0%
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0%

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Points for User
11
Points for Reputation
10
Points for every day since registration
1
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Points for threads
3
Points for Threads
1
Points for tagging threads
1
All Points for posts
Points for Posts
3
Points for Posts
3
All Points for miscellaneous
Points for Misc
0

Activities


6th October 2017
03:12 ranjithanih has earned 1 Points for User points

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