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andy2000a
Joined: 18 Jul 2001
Posts: 756
Helped: 7
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 03 Dec 2004 7:51 how to design low current regulator ?? |
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some LDO asic only work on < 10ua ..
how to design it ? regulator need OPA + bandgap ..
if bandgap total working current < 1u ,
cmos process design use BJT model (parasic device) can be use under
such small current ( maybe BJT current < 100na ) ??
I don't think FAB have good spice model for BJT device ..
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Fom
Joined: 10 Mar 2004
Posts: 758
Helped: 56
Location: Taiwan
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| 03 Dec 2004 8:18 Re: how to design low current regulator ?? |
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Recently I designed 3.3V LDO with Ignd=2uA and loading 40mA.
Yes, you are right: Bandgap about 0.5uA, resistor divider of regulator is about 0.3uA (3K poly resistor option) , and OP amp is about 0.6uA. I get a typical case Icc=1.42uA. The most problem frequency compensation (as usual).
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leo_o2
Joined: 03 Sep 2004
Posts: 330
Helped: 20
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| 03 Dec 2004 11:31 Re: how to design low current regulator ?? |
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Fom,
What current is your basic bias current?
So small current is suspected noise influence.
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cetc1525
Joined: 08 Oct 2004
Posts: 177
Helped: 3
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| 04 Dec 2004 15:03 how to design low current regulator ?? |
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I need to design a 3-terminal adjustable negative voltage regulator.I want to know yours suggestions.
please give me some .
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cmosbjt
Joined: 25 Apr 2004
Posts: 227
Helped: 8
Location: Boston
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| 08 Dec 2004 15:24 Re: how to design low current regulator ?? |
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| Fom wrote: |
Recently I designed 3.3V LDO with Ignd=2uA and loading 40mA.
Yes, you are right: Bandgap about 0.5uA, resistor divider of regulator is about 0.3uA (3K poly resistor option) , and OP amp is about 0.6uA. I get a typical case Icc=1.42uA. The most problem frequency compensation (as usual). |
Cool !! Will your design be turned into a real product or just a research project? Can you share more detail about your design? Such as what's the current for every branch (opamp 1st/2nd gain stage, two bjt branches in bandgap, current mirrors ......)? At this moment, I also want to reduce the power consumption of my design. Thanks.
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Fom
Joined: 10 Mar 2004
Posts: 758
Helped: 56
Location: Taiwan
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| 09 Dec 2004 2:34 Re: how to design low current regulator ?? |
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I am not sure that I can share details. My boss will fire me if he get to know about that. Because we designed that for another company and signed NDA.
I had no noise specs, so I didn't care about that.
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sunking
Joined: 25 May 2004
Posts: 914
Helped: 46
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| 09 Dec 2004 5:49 Re: how to design low current regulator ?? |
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| you can refer tolex LDO, which use depeltion nmos. The current as low as 2uA
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andy2000a
Joined: 18 Jul 2001
Posts: 756
Helped: 7
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| 09 Dec 2004 5:55 Re: how to design low current regulator ?? |
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Hi Fom
cmos bandgap only use 0.5um .. you have large resistor , how about your Vbg
> 1v or < 1v .. , which topology be used ??
OPA only 0.3ua is very small , I think BW is small or phaseMargin have problem
becuase this OPA need to drive output mos for LDO
.. how about this OPA spci ? offset <1mv
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Fom
Joined: 10 Mar 2004
Posts: 758
Helped: 56
Location: Taiwan
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| 09 Dec 2004 6:51 Re: how to design low current regulator ?? |
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BG is standard 1.25V.
OPA (or error amplifier) about 0.6uA (not 0.3uA).
The worst phase margin was about 25. It was simulated for all conditions, including process-voltage-temperature-load (both resistor and capacitor deviation) deviation.
Offset of error amplifier had minor effect than other factors.
What is OPA spci?
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xwcwc1234
Joined: 21 Jul 2001
Posts: 313
Helped: 5
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| 09 Dec 2004 6:57 Re: how to design low current regulator ?? |
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Hi Fom,
About your LDO , I have some questions:
(1) BG is standard 1.25V.
Did you use large resistor for reducing current ?
(2) OPA (or error amplifier) about 0.6uA (not 0.3uA).
The worst phase margin was about 25? Is it enough for application ?
(3) Did you use other special device in your circuit such as non-enhancement MOS ?
By the way , you got many points . Can denoated some points to me ? Thank you.
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survivor
Joined: 10 Aug 2004
Posts: 36
Helped: 3
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| 09 Dec 2004 17:03 how to design low current regulator ?? |
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Hi, Fom ;
Good job !
Do you use ratio BJTs to get PTAT voltage?
If yes, may you let us know the ratio? (1: or (1 ).
If no, what kind of ckt do you use to get PTAT voltage??
Besides, under such low current, most of the transistor will work under subthreshold region. Spice models with good accuracy will become a problem. May you share your experience on that during design consideration??
Thanks a lot for your answer : )
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