Special counter: set&reset triggered by rising edge of p

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Danielye

Joined: 10 Dec 2003
Posts: 29

02 Dec 2004 2:17 Special counter: set&reset triggered by rising edge of p

Could this counter can be implemented?

This counter has three input, reset (clear),set(stop the counter),clock,
I want all these inputs can triggered the counter by rising edge.
How to implement this logic? Could someone kindly provide the VHDL code?

Thanks a lot!

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Black Jack

Joined: 02 Dec 2003
Posts: 221
Helped: 11
Location: UKRAINE

02 Dec 2004 13:09 Re: Special counter: set&reset triggered by rising edge

Danielye wrote:

DDF with Synchronous Preset

Code:

library IEEE;
use IEEE.std_logic_1164.all;

entity act_dff_sync_pre is
port (data, clk, preset : in std_logic;
   q                : out std_logic);
end act_dff_sync_pre;

architecture behave of act_dff_sync_pre is
begin
process (clk)
begin
if (clk'event and clk = '1') then
   if (preset = '0') then
      q <= '1';
   else
      q <= data;
   end if;
end if;
end process;
end behave;

DDF with Synchronous Reset

Code:

library IEEE;
use IEEE.std_logic_1164.all;

entity act_dff_sync_rst is
port (data, clk, reset : in std_logic;
   q                : out std_logic);
end act_dff_sync_rst;

architecture behave of act_dff_sync_rst is
begin
process (clk)
begin
if (clk'event and clk = '1') then
   if (reset = '0') then
      q <= '0';
   else
      q <= data;
   end if;
end if;
end process;
end behave;

Black Jack

Joined: 02 Dec 2003
Posts: 221
Helped: 11
Location: UKRAINE

02 Dec 2004 13:18 Re: Special counter: set&reset triggered by rising edge

8-bit rising edge up counter with synch. reset, preset

Code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity counter is
port
(
   clk, set, rst : in std_logic;
   count       : out std_logic_vector (7 downto 0)
);
end counter;

architecture behave of counter is
signal cnt: std_logic_vector (7 downto 0);
begin
process (clk, cnt, rst, set)
   begin

      if (clk'event and clk = '1') then
         if (rst = '0') then
            cnt <= (others => '0');
         elsif (set = '0') then
            cnt <= (others => '1');
         else
            cnt <= cnt + '1';
         end if;
      end if;
end process;
      count <= cnt;
end behave;

Git

Joined: 12 Dec 2001
Posts: 1118
Helped: 1
Location: Torino

02 Dec 2004 13:36 Re: Special counter: set&reset triggered by rising edge

You could use a single JK flip flop to do that. Just drag one into a schematic and see what code it generates for an idea of how to implement it in VHDL.

Code:

architecture Behavioral of fjkc is
begin
process (C, CLR)
begin
if (CLR=’1’) then
Q <= ’0’;
elsif (C’event and C=’1’) then
if (J=’0’) then
if (K=’1’) then
Q <= ’0’;
end if;
else
if (K=’0’) then
Q <= ’1’;
else
Q <= not Q;
end if;
end if;
end if;
end process;
end Behavioral

Git