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bimbla
Joined: 13 Jul 2001
Posts: 536
Helped: 13
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 01 Dec 2004 5:47 Clock design using PLL |
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What is the best way to get a stable clock of 25MHz and 12.288Mhz?
Can I use a 27MHz crystal and a PLL? What will be the guidelines?
(I have no access to 25MHz and 12.288MHz crystals)
bimbla.
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huanchou
Joined: 23 Aug 2004
Posts: 44
Helped: 2
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| 02 Dec 2004 5:44 Re: Clock design using PLL |
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If you want use the 27MHz crystal and pll to generate the 25MHz clock, try to use the pre-divider=7 loop-divider=13 post-divider=2 so that the output clock will be 27MX13/(7X2)≈25MHz in 5000ppm.
If you want to generate the 12.288MHz try to use the pre-divider=45 loop-divider=41 post divider=2 then you will get the output freq.≈12.288 in 1000ppm.
The two freqs. somewhat like the audio spec.
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bimbla
Joined: 13 Jul 2001
Posts: 536
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| 02 Dec 2004 6:25 Re: Clock design using PLL |
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They are freq. related to audio.
I am a starter in PLL design. Could you...well spoon feed me a little more?
I would appreciate it if you could refer some reading material also. I pick up well.
Who makes some popular PLL blocks?
Thanks in advance.
bimbla.
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huanchou
Joined: 23 Aug 2004
Posts: 44
Helped: 2
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| 02 Dec 2004 9:31 Re: Clock design using PLL |
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The attached picture is the popular PLL block for your reference.
You can find the sub-block circuit in IEEE paper.
The AN535 is a good reference.
http://www.freescale.com/files/rf_if/doc/app_note/AN535.pdf
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platonas
Joined: 14 Aug 2004
Posts: 165
Helped: 5
Location: Universal Citizen
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| 06 Dec 2004 11:23 Re: Clock design using PLL |
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Another method to have your desired frequency is to usee some special ICs fro Cypress. One such IC is the CY22393. More info on [url]h**p://www.cypress.com/[/url]
[/url]
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yaxazaa
Joined: 13 Nov 2004
Posts: 116
Helped: 3
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| 07 Dec 2004 8:22 Re: Clock design using PLL |
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| If you use crystal, you still need design on-chip oscillator. Otherwise, crystal is not able to drive. PLL is a good way to do it. To design such low frequency PLL, you may need to pay attention to the charge-pump if you are using charge-pump based PLL.
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jswei303
Joined: 02 Nov 2004
Posts: 23
Helped: 1
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| 08 Dec 2004 8:23 Re: Clock design using PLL |
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hi...
On Audio application, the PLL jitter is not so important as its precision.
you might choose a set of division numbers well to fit the requirement.
And you use external Cap or internal ones?
that affect your chip size much
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jswei303
Joined: 02 Nov 2004
Posts: 23
Helped: 1
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| 08 Dec 2004 8:24 Re: Clock design using PLL |
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hi...
On Audio application, the PLL jitter is not so important as its precision.
you might choose a set of division numbers well to fit the requirement.
And you use external Cap or internal ones?
that affect your chip size much
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huanchou
Joined: 23 Aug 2004
Posts: 44
Helped: 2
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| 08 Dec 2004 12:14 Re: Clock design using PLL |
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| I agree the JSWEI303 saying. So I suggest that the pre-divider don't have too large N number, or the loop filter will be large that will waste many chip area.
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arsenal
Joined: 17 Oct 2004
Posts: 134
Helped: 11
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| 09 Dec 2004 3:41 Clock design using PLL |
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| i think if the predivider has a too large N then the noise will be great
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andy1
Joined: 24 Jul 2004
Posts: 124
Helped: 2
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| 13 Dec 2004 0:57 Re: Clock design using PLL |
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| I would recommend using a crytal at multiple of your target frequencies. Too many divider will be a nightmare you try to meet jitter spec.
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cirand
Joined: 27 Aug 2003
Posts: 30
Location: China
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| 13 Dec 2004 2:46 Re: Clock design using PLL |
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| why not use 24.576Mhz crystal, ?
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