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andy2000a
Joined: 18 Jul 2001
Posts: 756
Helped: 7
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 29 Nov 2004 11:11 how to design cmos high speed analog comp |
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vcc=3.3v ~ 12v , and compare volt=500mv , delaytime < 5ns
and input is pulse signal < 10ns , no clock signal for latch
how to design this high speed comparate ?
which topology be suit ? 2_stage or foldcascode ?
I think 2 stage is small area but speed is slow ..
thank you
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andy2000a
Joined: 18 Jul 2001
Posts: 756
Helped: 7
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| 29 Nov 2004 11:30 Re: how to design cmos high speed analog comp |
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by the way , if we use 2 stage OPA-> comparator
can we meet delay time < 20ns ..
I think 2 stage OPA is easy design than others..
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gevy
Joined: 17 Nov 2004
Posts: 377
Helped: 41
Location: Russia
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| 29 Nov 2004 13:06 Re: how to design cmos high speed analog comp |
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| I think, that is necessary to use the following cascades: folded cascode, current comparator and digital inverters series connected.
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konqueror
Joined: 27 Nov 2004
Posts: 93
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| 29 Nov 2004 16:07 Re: how to design cmos high speed analog comp |
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in 2 stage comparator speed is less so
use a regenerative(hysteresis) comparator.
it can give u very fast speeds.u can refer to
"cmos analog circuit design" by
allen & hollberg for designing details of
comparators with hysteresis
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CDRCDR
Joined: 15 Feb 2004
Posts: 82
Helped: 2
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| 13 Dec 2004 0:07 how to design cmos high speed analog comp |
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| I would recommend a preamplifier and then followed by latch circuit
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yeewong_su
Joined: 12 Oct 2004
Posts: 126
Helped: 3
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| 13 Dec 2004 1:30 how to design cmos high speed analog comp |
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2 stage simple opamp and inverter driver output.
latch circuit will add it's difficult
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Colbhaidh
Joined: 10 Aug 2004
Posts: 151
Helped: 16
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| 13 Dec 2004 11:40 Re: how to design cmos high speed analog comp |
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Vcc = 3V3 -> 12V !! Are you sure ????
This is impossible in CMOS !!
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qslazio
Joined: 23 May 2004
Posts: 194
Helped: 8
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| 13 Dec 2004 11:50 how to design cmos high speed analog comp |
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| simple preamp and 2 inverter will meet your requirement
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james_su
Joined: 14 Dec 2004
Posts: 4
Helped: 1
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| 14 Dec 2004 1:34 how to design cmos high speed analog comp |
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| Don't use the latch ckt if you not use the clock signal
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icsrc
Joined: 14 Dec 2004
Posts: 10
Helped: 2
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| 14 Dec 2004 13:26 how to design cmos high speed analog comp |
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| i've never seen 12V supply in CMOS process
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electronrancher
Joined: 24 Mar 2002
Posts: 474
Helped: 34
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| 15 Dec 2004 0:29 how to design cmos high speed analog comp |
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Please guys - the post is about comparators, not whether you have personally seen a 12v gate. I have a process with 5v, 16v, and 30v gates that I use quite often. I suggest you guys keep looking.
back to Andy's question....
The trick will be keeping the (Internal) voltage swings small in order to be fast. Current comparator style is OK, but clamp the nodes so they can't swing Vdd-GND else it will be very slow.
I am thinking of a cascade of 3 low-gain (10 or less) diff amps (outputting to resistors), then a low-voltage to high-voltage translator. The final output would be an inverter. The trick is you need to drive that inverter's gate from 0-VDD, but the output of the last diff stage is probably 0-1v. You could use two NMOS to flip a level-shift, but I don't know if it would be fast enough.
You could probably get through the diff amps in 2-3ns, but driving that output inverter may be slower than you can tolerate.
The Li book (CMOS ckt dsn, simulation, and layout) has a 10ns comparator that may work for you if you can't get a 2ns level shift.
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