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beckwang
Joined: 04 Aug 2004
Posts: 4
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 27 Oct 2004 11:46 Memory Design |
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Who can tell about Mirror Bit flash memory of AMD?
I am a memory designer, and want to exchange some experience. thanks!
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mike_bihan
Joined: 21 Mar 2002
Posts: 259
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| 28 Oct 2004 7:47 Memory Design |
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| I am interested too.
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Colbhaidh
Joined: 10 Aug 2004
Posts: 151
Helped: 16
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| 28 Oct 2004 8:47 Re: Memory Design |
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This is a patented layout whereby the control gate of the flash cell combined with two opposing source and drain connections can be used to place charge on the nitrided gate on either side. I do not "yet" have access to the layout but a simple way to visualise this is two vertical strips of active area and one horizonal strip of Control Gate poly. You can charge up the LHS of the floating gate using the LHS Source and Drains as conventional flash. Same for the RHS. Making sure the Source Drain sides are opposite you can isolate the charge in the floating gate to the LHS or RHS. So effectively you have the same effect as two independent cells sharing the same control gate and floating gate. This is much better than using the multi level charge scheme where 4 bits can be stored in one cell but requires 4 comparators per sense amp. The mirror bit does not require any fancy sense amps.
So effectively you have (looking top down) .......
D S
Nitirided gate oxide ++++ ---------
Poly Control gate =====================
Nitirided gate oxide ++++ ---------
S D
but of course considerably smaller than this (eg same cell size as conventional cell - ish )
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