Could Verilog modules used together with VHDL modules?

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walkon

Joined: 21 Oct 2004
Posts: 20

24 Oct 2004 8:02 Could Verilog modules used together with VHDL modules?

Could I use a Verilog module to drive a VHDL model?
Because I want to present real numbers, but it seems Verilog
even couldn't support the real array. So could I use a VHDL
to do the computation with real numbers driven by a Verilog module?

Thanks.

davorin

Joined: 07 Jun 2003
Posts: 1396
Helped: 8

24 Oct 2004 9:26 Re: Could Verilog modules used together with VHDL modules?

Several packages support mixed language entries like Altera qu(at)rtus, Xilinx ISE and Synplify Pro...ispLever doesn't...

Already discussed few times here...have you searched before posting your question? I guess not (o;

And tell me..why did you post the question in "Analog circuit design" ????

vaf20

Joined: 27 Jan 2003
Posts: 173

24 Oct 2004 13:10 Re: Could Verilog modules used together with VHDL modules?

two questions:
1- what's ispLever?
2- can this mixed mode been synthesised?
tnx

davorin

Joined: 07 Jun 2003
Posts: 1396
Helped: 8

24 Oct 2004 13:58 Re: Could Verilog modules used together with VHDL modules?

Quote:

two questions:
1- what's ispLever?

Software tool from Lattice for their devices. Could have been answered via a quick google search!

Quote:

2- can this mixed mode been synthesised?

What do you think it means when I say above tools mentioned support mixed languages? They are "synthesizing" tools!!

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24 Oct 2004 13:58 Ads

walkon

Joined: 21 Oct 2004
Posts: 20

25 Oct 2004 0:22 Re: Could Verilog modules used together with VHDL modules?

hi, Thanks for u reply very much.
secondly, I just realized that I posted in the wrong board.
I try to find my post on Analog Circuit Design just now. hehe
I thought I posted there, but seems not.
I am sorry for the inconvience I brought.

walkon

Joined: 21 Oct 2004
Posts: 20

25 Oct 2004 1:03 Re: Could Verilog modules used together with VHDL modules?

And, by looking back to the previous discussion, I get the idea that it could work.

And the reason why I need to use VHDL is because I want to process some real numbers. And could the ports in Verilog be defined as the format of real arrays?

ram

Joined: 03 May 2004
Posts: 118
Helped: 4

15 Dec 2004 9:49 Could Verilog modules used together with VHDL modules?

Yes you can use with cadence

nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

15 Dec 2004 10:11 Re: Could Verilog modules used together with VHDL modules?

You can use module port to output real no.s in verilog
for that you need to use $bitstoreal and $realtobits system functions!
Check with Cadence verilog users guid