electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

'signal' (vhdl) = 'wire' or 'reg' (verilog)
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> 'signal' (vhdl) = 'wire' or 'reg' (verilog)
Author Message
davyzhu



Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental
Post21 Oct 2004 6:02   

vhdl wire
Hello all,

I found vhdl use signal and verilog use wire and reg to describe a connection between combinational logic, but the thing bothered me that "how to specify the signal to be wire or reg" or " signal equal to wire or reg" ? Rolling Eyes

Regards,

Davy Zhu
Back to top
eda_wiz



Joined: 07 Nov 2001
Posts: 720
Helped: 30
Post21 Oct 2004 10:17   

vhdl reg
davyzhu..
I guess u r trying to convert some VHDL to verilog. Well a signal in VHDL can be reg or wire in verilog.. ie if the signal is intended to be synthesised as a flop .. it shud be reg... else wire...
Inside the "process" statement , if any signal is assigned to any other signal it will be flop .. or if outside process it will be a net..

hope this helps

Last edited by eda_wiz on 02 Apr 2006 11:47; edited 1 time in total
Back to top
Google
AdSense
Google Adsense
Post21 Oct 2004 10:17   

Ads


Back to top
craftfox



Joined: 18 Mar 2004
Posts: 82
Helped: 2
Post22 Oct 2004 4:39   

verilog wire reg
I think u have had a vhdl version in your hand. You can analysis the function of the vhdl module. None fixed relation.
Back to top
presto



Joined: 26 Nov 2001
Posts: 39
Post26 Oct 2004 0:33   

verilog reg in vhdl
whizkid wrote:
davyzhu..
I guess u r trying to convert some VHDL to verilog. Well a signal in VHDL can be reg or wire in verilog.. ie if the signal is intended to be synthesised as a flop .. it shud be reg... else wire...
Inside the "process" statement , if any signal is assigned to any other signal it will be flop .. or if outside process it will be a net..

hope this helps

regards
WHIZKID


In Verilog, 'reg' does not have to be synthesised as flop or latch, even when it's in the 'always' statement. Also, I wondered if 'signal' in the 'process' in VHDL was always synthesised into flop or latch? As I just started to use VHDL, will any VHDL guru clarify this point? cheers
Back to top
bibo1978



Joined: 01 May 2004
Posts: 229
Helped: 6
Post27 Oct 2004 5:01   

wire in vhdl
I believe that there is no straight forward relation however, I yoou can use this rule, if the signal is synthesized as a register or latch, then use reg otherwise use wire, I believe it is this simple.

However Iwant to note that not all process in VHDL produce a reg. or latch but it depends on two things, 1- the sensitivity list, 2- wether all conditions of changes were included in the process code area.


thats all folks
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> 'signal' (vhdl) = 'wire' or 'reg' (verilog)
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
reg & wire (12)
Difference between reg and wire (15)
about wire and reg in instantiation (4)
Query regarding wire and reg (2)
Avoid reg/wire optimization in FPGA synthesis (1)
Need complex VHDL/Verilog codes (more than 1 clock signal)? (1)
how to dump all signal waveform when import VHDL int Verilog (5)
VHDL to Verilog and Verilog to VHDL Converter (13)
REG case statement in verilog (2)
about the reg in verilog (2)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS