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electronrancher
Joined: 24 Mar 2002
Posts: 474
Helped: 34
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 16 Oct 2004 3:36 fast cmos comparator with LOW IDD? |
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fastest i can get is about 20ns with a 4-stage running off 5v VDD. Only problem is the Q current is 100uA.
I'd trade 10-20ns to cut that current down - anyone good at cmos comps? i find the slowest stage is the final stage that needs to switch from 0-VDD, anyone have creative solution for this?
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devrimaksin
Joined: 13 Oct 2004
Posts: 93
Helped: 9
Location: Dallas, Texas, USA
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| 16 Oct 2004 6:37 fast cmos comparator with LOW IDD? |
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Do you need a continous comparator or
clocked comparator is ok?
If so, you can go much faster and (<10ns)
with much less quiesscent current (10uA)
Another thing, is hysterisis ok? if so again
you can use cross coupled positive feedback
load to improve (speed/Iqq) ratio.
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electronrancher
Joined: 24 Mar 2002
Posts: 474
Helped: 34
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| 16 Oct 2004 7:00 fast cmos comparator with LOW IDD? |
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not clocked, but a little hystereisis (10-50mV) is always welcome.
on the topic of clocking, i have only seen fast clocked comparators when used in applications such as ADC, where a bank of comparators is strobed at the sampling instant, and all the values are read in parallel.
in my application, I will probably disable or reset the comparator for about 50ns, but then i need it to be active for about 250ns while my signals move around. if they cross at 60ns or 299ns i still need to trigger, so flash ADC comparators aren't good for me. continuous comparator most likely, but i will add a reset/shutdown regardless.
are you're a comparator guy?
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devrimaksin
Joined: 13 Oct 2004
Posts: 93
Helped: 9
Location: Dallas, Texas, USA
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| 17 Oct 2004 2:22 fast cmos comparator with LOW IDD? |
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I am rather an ADC guy.
Well, you can obtain best speed/propagation delay ratio from
clocked comparators (If you have fast clock within the system,
it is going to be equivalent to sampling). For the positive feedback load (if you use), be sure that you chose the transconductance of the cross coupled devices is equal to the diode connected load transistors. (if you go through the small signal analysis, you will find out that the gain is
gm_in/(gm_diode-gm_cross)) so the fastest operation condition occurs
when gm_diode is equal ot gm_cross
Good luck, it is not easy to design continous time comparator fast and low power.
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cetc1525
Joined: 08 Oct 2004
Posts: 177
Helped: 3
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| 24 Oct 2004 7:23 fast cmos comparator with LOW IDD? |
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| I think I can use it to design my project.
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