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srivatsan
Joined: 04 Aug 2004
Posts: 183
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 10 Oct 2004 20:08 Need help in analysis. |
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What are Fast NMOS, slow PMOS; FNFP, SNFP, SNSP? I have no idea... whoever has worked on them. please reply.
thanks
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yorande
Joined: 19 Jan 2004
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| 11 Oct 2004 5:52 Re: Need help in analysis. |
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Those are terms concerning the manufacture technology.
Well, variation of the parameters of the MOSs I think.
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Hughes
Joined: 10 Jun 2003
Posts: 712
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| 11 Oct 2004 6:04 Need help in analysis. |
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| Fast model and slow model are different in Vth, Idsat, etc., resulting in process varations such as varation in tox, Nsub.
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santhoshv78
Joined: 22 Jun 2004
Posts: 72
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| 11 Oct 2004 7:41 Re: Need help in analysis. |
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These are used in the model files to simulate the MOS for the corner conditions.
for slow mos, the thresold voltage is increased and for fast MOS, the thresold voltage is decreased. Other variations could be tox, junction capacitances..etc
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hrkhari
Joined: 04 Mar 2004
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| 11 Oct 2004 7:49 Re: Need help in analysis. |
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Hi:
It is more to the process variation, the designed circuitry should be well operated in all of this condition in a satisfactory output prior to GDSII submission
Rgds
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srivatsan
Joined: 04 Aug 2004
Posts: 183
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| 11 Oct 2004 19:41 Re: Need help in analysis. |
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Hence use the process corner parameters (which models the FF, FS, SF, SS) and then verify the circuit.
But this now increases the number of testing in exponentially (exponent = 4). Therefore it is illogical and waste of time. So how to determine which oprational mode and/or transistor can be affected by each and every process corners? If it is not clear: For every FF...SS, there is some inteneded operation is being affected (due to change in transistor characteristics). How to spot them? REply if you have done before. Thanks in advance.
Srivats
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radiohead
Joined: 13 May 2004
Posts: 331
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Location: Heart of Europe
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| 11 Oct 2004 22:52 Re: Need help in analysis. |
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These are just cornercases. As you know, processes have tolerances from wafer to wafer and even over one wafer. These changes result in different Cox, Vth, tox, .... The process has upper and lower limits for every one of these parameters. The slow model is the transistor model, where every parameter is at its limit where it makes the transistor the slowest. The fast model is exactly the opposite.
In real life you would probably never get into these extreme corner cases. These are only error checks, mostly used by digital designers to test their gates under any possible circumstance.
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srivatsan
Joined: 04 Aug 2004
Posts: 183
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| 12 Oct 2004 1:19 Re: Need help in analysis. |
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Well, I was just curious how these process corners affect my analog circuit? i understand more of those process corners.. finally, if anyone has found any kind of relationship between those corners and analog circuits.. let me know. thanks in advance.
thanks for all those replies.
srivatsan
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