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mohdfaaf
Joined: 26 Sep 2004
Posts: 23
Location: malaysia
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 29 Sep 2004 9:57 question on mixed signal using cmos |
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Question: I read somewhere says
"CMOS Analog circuits require transistors with low output conductance (gds) in order to achieve high gain. Submicron MOSFETs with halo implants and retrograde wells are designed to have high transconductance (gm) but often suffer from poor output conductance".
What is rout and why is it important for analog cmos? How by adding halo implants will have worse rout...
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krashkealoha
Joined: 03 Jul 2004
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Location: 21.402, -157.739
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| 29 Sep 2004 23:37 Re: question on mixed signal using cmos |
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Rout is the change in Vds divided by the change in Idrain. From a designers point of view, it is desired to have a high Rout because it allows a constant Idrain with changing Vds. This is ideal for current mirrors, which will source a constant current over voltage supply variations. To achieve high Rout, one has to minimize the channel-length modulation.
I'm not an expert in halo-implants, but I will try to relate it to halo-implants. Halo-implants minimizes threshold voltage roll-off as the gate length is scaled down. A smaller gate length is one of the factors of increasing the gm of the transistor. In addition, the halo-implant creates a more abrupt drain-channel junction because of the lower channel concentration. The lower channel concentration leads to higher mobility in the channel which increases the transconductance of the transistor.
Because of the abrupt drain-channel junction along with the ability to scale down to shorter channel lengths, this increases your channel-length modulation, which then degrades Rout.
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mohdfaaf
Joined: 26 Sep 2004
Posts: 23
Location: malaysia
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| 30 Sep 2004 9:57 Re: question on mixed signal using cmos |
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Thanks for your explanation. I agree with you on Rout where Rout for analog device is desired to be as high as possible.
However, for halo implants, I have to disagree. halo implants used basically to suppress the short channel effects. halo implants use same dopant species as channel , and by adding it, we increase the channel dopant concentration. that is why you will see higher vt as vt itself is a function of channel dopant concentration.
by adding halo implant near to S/D, the depletion region will be smaller and like you said you will see a more abrupt junction, thus minimizing the effect of dpeletion region modulation ( which will cause punchthrough or higher leakage if there is no halo implant ).
So, the part that I am still not clear is how does the halo implant degrades the Rout. If I am not mistaken, I read somewhere ( correct me if I am wrong ) that halo implant will create ununiform channel from S to D. But I dont know how this can be related to the degradation.
thanks.
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krashkealoha
Joined: 03 Jul 2004
Posts: 101
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Location: 21.402, -157.739
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| 30 Sep 2004 16:31 Re: question on mixed signal using cmos |
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Thanks for clarifying what the effect of a halo implant is. Sorry I'm not able to explain it with respect to device physics.
I saw this paper which hopefully someone can post it for us...
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 1
Chapter 11: Wafer and MEMS Processing
Title: Process Factors in the Reduction of Output Conductance in Sub-micron CMOS
Authors: N.C. May, H.S. Tan and A.V. Kordesch
Affilation: SILTERRA (M) SDN BHD, MY
Pages: 477 - 480
Keywords: output conductance, early voltage, DIBL, Rout, channel engineering
Abstract: CMOS Analog circuits require transistors with low output conductance (gds) in order to achieve high gain. Submicron MOSFETs with halo implants and retrograde wells are designed to have high transconductance (gm) but often suffer from poor output conductance. In this paper we investigated the process factors affecting gds and we show how to optimize gds. Our experimental results from 180nm CMOS are compared with 2D simulations in order to understand the mechanisms involved. Output conductance is the derivative of the ID-VD curve, gds = dID/dVD. In saturation, several effects contribute to the increase of ID with VD, namely channel length modulation (CLM), drain-induced barrier lowering (DIBL), and substrate current body effect (SCBE). We have mainly focused on PMOS transistors at voltages where the substrate current is not significant.
ISBN: 0-9728422-7-6
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mohdfaaf
Joined: 26 Sep 2004
Posts: 23
Location: malaysia
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| 30 Sep 2004 17:16 Re: question on mixed signal using cmos |
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Yes, I am also hoping anyone who has anything on this to post in the forum.
I am wondering, if rout degradation due to halo / retrograde implants will limiting the cmos analog scaling.. what's next since those implants are well known for short channel device.
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