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jordan76
Joined: 25 Mar 2004
Posts: 177
Helped: 4
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 10 Sep 2004 10:06 how many ways to reduce power bus spike? |
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Hi guys,
As we know, decoupling cap is certainly one way among them,but it also increase the total power consumption. Any other good means to achieve low power bus spike and low power consumption at the same time?
Any inputs/comments are appreciated. Thanks!
regards,
jordan76
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jay_ec_engg
Joined: 19 Jun 2004
Posts: 157
Helped: 1
Location: India
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| 10 Sep 2004 10:33 Re: how many ways to reduce power bus spike? |
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| u can put power line and ground line as close as possible to reduce spikes....
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dumbfrog
Joined: 17 Jul 2004
Posts: 191
Helped: 4
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| 10 Sep 2004 17:34 Re: how many ways to reduce power bus spike? |
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reduce your current loop "AREA" for power and ground=lower L (L is a function of loop "AREA")
Vspike=Ldi/dt
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jordan76
Joined: 25 Mar 2004
Posts: 177
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| 11 Sep 2004 11:00 Re: how many ways to reduce power bus spike? |
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Thanks for your replies!
Could you give some more details?
Also if the circuit toggles frequently between operation mode and sleep mode,how to reduce power bus spike?
regards,
jordan76
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Mr.Cool
Joined: 20 Jun 2001
Posts: 526
Helped: 16
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| 11 Sep 2004 15:41 Re: how many ways to reduce power bus spike? |
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to protect against voltage spikes you could place a transorb between the rail & ground. this is very very low power consumption because it only conducts during a spike, which is very short period of time.
and decoupling caps hardly take any power consumption, though i guess this is relative. choose a cap with very low ESR value may help. tantelums are always nice
Mr.Cool
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jordan76
Joined: 25 Mar 2004
Posts: 177
Helped: 4
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| 12 Sep 2004 3:31 Re: how many ways to reduce power bus spike? |
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Mr.Cool,
Thanks for your input! But I mean power bus spike inside IC instead of PCB.So tantelums are beyond our options...
True, deccoupling cap is usually a good option for reducing power bus spike if its power consumption is tolerable. But for power critical applications like mobile phone etc, too much decoupling cap will kill its limited power budget. Thus, we need to find an alternative to achieve both low power bus spike and low power consumption.
Any inputs/comments are welcome. Thanks.
regards,
jordan76
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faisal78
Joined: 27 Aug 2004
Posts: 6
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| 16 Sep 2004 4:19 Re: how many ways to reduce power bus spike? |
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Can you help me better understand this as this is probably more related to IC silicon design which I am intrested in.
How does adding bypass caps. increase power consumption? Pulldown/up resistors makes sense, but capacitors?
How does ESR affect this parameter? 
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jordan76
Joined: 25 Mar 2004
Posts: 177
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| 16 Sep 2004 11:20 Re: how many ways to reduce power bus spike? |
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Suppose you turn on and turn off your mobile phone frequently,
it will also dissipate heat gradually,right?
The larger the decoupling cap,the bigger the power consumption.
regards,
jordan76
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djalli
Joined: 10 Nov 2001
Posts: 887
Helped: 15
Location: 1600 Pennsylvania Avenue, Washington DC 20500
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| 17 Sep 2004 13:46 how many ways to reduce power bus spike? |
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You are looking of how many ways?
What is your design? I can make a suggestion because if I make this way (as shoot in the dark) always is chance to suggest the general one or worse to suggest the wrong one.
Initial schematic also would be great.
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Borber
Joined: 01 Jan 1970
Posts: 1485
Helped: 111
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| 17 Sep 2004 14:30 Re: how many ways to reduce power bus spike? |
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| Your problem is trivial. If someone has a lot of conversation he will discharge battery very fast. Taking into account transitional effect of charging bypass capacitors to battery life expectancy during switch on is negliglible except you want to go to extremes.
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terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
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| 03 Oct 2004 5:56 Re: how many ways to reduce power bus spike? |
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| How can decoupling capacitors consumed power? I think decoupling cap consumption is neglible, unless during the turn on and turn off of the mobile phone since there must be some initial current to be charge on the caps (yes, it's true that power consumption will be increase significantly only if you switch on and off the mobile phone by hand as fast as the sampling frequency used in your mobile phone......)
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jordan76
Joined: 25 Mar 2004
Posts: 177
Helped: 4
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| 10 Oct 2004 6:42 Re: how many ways to reduce power bus spike? |
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Sorry for the confusion by my cell phone example.
Let me ask in another way:
What is the maximum/optimal decoupling capacitance value you can accept to reduce power bus spike?
regards,
jordan76
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binu G
Joined: 09 Jan 2003
Posts: 728
Helped: 9
Location: Bangalore
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| 10 Oct 2004 8:32 how many ways to reduce power bus spike? |
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what type of decoupling cap will be suitable different frequency gradient?
Regards
binu G
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terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
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| 10 Oct 2004 9:51 Re: how many ways to reduce power bus spike? |
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| The optimal decoupling capactiance value depends on the amount of digital current spike generated in the supply rail at any time. I think a model can be constructed with including the decoupling cap and package inductance to simulate how much decoupling cap is enough to reduce the current spike to an acceptable level. Probably if you use MOSCAP, typically 100 - 200 pF (depends on your die area)
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binu G
Joined: 09 Jan 2003
Posts: 728
Helped: 9
Location: Bangalore
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| 10 Oct 2004 15:10 how many ways to reduce power bus spike? |
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I mean what type of material like ceramic, tandalam and so on?
i would like to know the frequency band width of these base material.
tandalam is suggested in which frequency range.
or it is applicable to any freqency rang.
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