What is a function of PLL and DLL in FPGA ??

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jay_ec_engg

Joined: 19 Jun 2004
Posts: 157
Helped: 1
Location: India

08 Sep 2004 4:59 dll fpga

Hi..
what is a function of PLL and DLL in FPGA.. while selecting FPGA... which specifications related to PLL and DLL I should keep in mind.
Can anyone give me some example where PLL and DLLs have played critical role in designing ?

brmadhukar

Joined: 21 Jun 2002
Posts: 844
Helped: 29

08 Sep 2004 5:48 fpga dll

When you need clock frequencies that are say 3 times greater than your fundamental clock you may use the clock multiplier block and this will save you an extra clock and also provides synchronization. These blocks use DLLs. PLLs are not as important. They may may be approximated closely by DLL.

So If your appln requires a syncronized higher multiple of your clock use FPGAs that support DLL.

B R M

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jay_ec_engg

Joined: 19 Jun 2004
Posts: 157
Helped: 1
Location: India

08 Sep 2004 6:46 dll in fpga

first of all thanks...
Actually I dont know how to use this feature in FPGA... I worked with altera FPGAs... but i never used thsi tech... and dont know how to use DLL and PLL... How can it multiply clocks ??
please guide me.. it willbe very helpful to me in my present project also...

I heard that some IDT Zero Delay Buffers are also available which wil give u same clocks ( i mean from 1 clock sourse u will get 4 clks as o/p).. so if pin is not a constraint in ur FPGA then i used this tech..

even after deviding a clock inside FPGA.. u used to take it outside as o/p and then again i gave it to the next block as i/p ( physically shorted i/p pin and o/p pin)...Someone told that its better it u do that... how true it is ?

silencer3

Joined: 03 Jun 2003
Posts: 110
Helped: 6

08 Sep 2004 10:19 difference between pll and dll

PLL and DLL are used to multiply and devide the input clock frequency given to fpga with or without a phase shift in the resultatnt clock.

For xilinx devices goto DCM (Digital Clock Manager) in the coregen to use the fpga PLL or DLL. For actel devices, please goto PLL usage area of their user manual.

tom123

Joined: 04 Apr 2005
Posts: 116
Helped: 3

18 Jun 2005 7:07 choosing high frequency clock for pll

PLL and DLL are used to compensate clock input buffer and

clock tree's delay, by using DLL or PLL, a clock input's active edge

and internal DFF's clock edge will occur simutaneously.

that improve IO timing dramatically and ease interface between fpga

and other ASIC chips.

best regards

jay_ec_engg wrote:

realtek

Joined: 16 Mar 2004
Posts: 101

21 Jun 2005 17:25 difference between pll and dll + fpga

Depend on your system need a clear clock source or not
if you working on High-Frequency(> 68 or 100M)
and it's a sync-system( ex: Sonet....)
you need a PLL (select Altera 20Kxxx or above)
if not ( some system use RC is enough), you dont need a PLL.

arunragavan

Joined: 01 Jul 2004
Posts: 487
Helped: 21
Location: India

21 Jun 2005 20:22 fpga+dll

actually you can construct ur own PLL infact ADPLL wud be appropriate.. I wud say it would be best if u designed it urself.

a general PLL structure wud have phase detector, a low pass filter and a VCO.

h**p://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

take a look at this..

wud help u

with regards

dBUGGER

Joined: 18 Apr 2005
Posts: 108
Helped: 12
Location: Milky Way

22 Jun 2005 8:06 fpga + dcm + dll

Well the pll's and dll's do many jobs in the FPGA or ASIC. They are used to multiply a clock frequency, divide it, provide a phase shifted version of a clock etc. and yes of course a very low skew clock o/p.
The frequency multiplication is must be achieved with the help of a high frequency oscillator inside(although no vendor tells how it is done !!!!!). The phase shifted clock can be used to interface with other components onboard, where you can just delay your clock by some time so that the trace length of the PCB will not add extra delay and your system be fully synchronized with respect to the main clock.
For the difference between PLL and DLL you can refer to any xilinx device user guide. Thank you.