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naomi
Joined: 04 Sep 2004
Posts: 9
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 06 Sep 2004 7:11 sigma delta ADC |
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can any one tell me what exactly the decimation filter is? and can we design the decimation filter in CMOS or its only with DSP?
what is meant by undersampling??
thank u
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naomi
Joined: 04 Sep 2004
Posts: 9
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| 06 Sep 2004 7:27 Re: sigma delta ADC |
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| can u suggest any ebooks on this topic please.........
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claint
Joined: 21 May 2004
Posts: 99
Helped: 2
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| 06 Sep 2004 12:13 Re: sigma delta ADC |
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| decimation filter is designed in digital domain
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eda4you
Joined: 17 Sep 2002
Posts: 283
Helped: 17
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| 06 Sep 2004 12:19 Re: sigma delta ADC |
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If you use in a sigma-delta modulator a comparator (=1 bit depth), the outputstream delivers only a single bit data. Due to oversampling you have the information for instance 1024 bit lenght. So you have to average the outputstream over time, and this is made during decimation. There are a lot of realization and often you have to take the droop of the sinc (=comb- , average- filter) into design consideration. It's most likely a FIR filter due to the linear phase = constant group delay.
Such filters are easy to realize using a cascade of int and diff!
Besides, the meaning of the word UNDERSAMPLING results from the fact that you reduce the sampling rate as in our example: 1bit(at)10*Fs to 10 bit(at)Fs
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naomi
Joined: 04 Sep 2004
Posts: 9
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| 07 Sep 2004 4:42 sigma delta ADC |
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hello sir
Thank you very much for the reply i could now understand how the decimation filter works.
As you have said it is easy to implement the comb filter in cadence can you please suggest me how to proced that in cadence.can you give me any referece for that as i could find that only using DSP implementation.
thank u very much
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dpsman
Joined: 23 Feb 2003
Posts: 89
Helped: 9
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| 07 Sep 2004 6:35 Re: sigma delta ADC |
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| Do you have MAT*LAB?? There is a pretty example in symulink about Delta Sigma modulation, decimation and etc.. There you can see it very "graphical"
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jay_ec_engg
Joined: 19 Jun 2004
Posts: 157
Helped: 1
Location: India
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| 07 Sep 2004 7:04 Re: sigma delta ADC |
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| U can use MATLAB for generating co-efficients for decimation filter... quantise it...and use them in FPGA memory.... or nowdays ready made tools are also available who will generate co-efficients.. tore in the internal ROM of FPGA and generate full VHDL prog also..... these tools are free.
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eda4you
Joined: 17 Sep 2002
Posts: 283
Helped: 17
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| 07 Sep 2004 13:40 Re: sigma delta ADC |
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| naomi wrote: |
hello sir
Thank you very much for the reply i could now understand how the decimation filter works.
As you have said it is easy to implement the comb filter in cadence can you please suggest me how to proced that in cadence.can you give me any referece for that as i could find that only using DSP implementation.
thank u very much |
Hi Naomi,
first you may ask yourself if you need a one chip solution or not. Implementing it in Cadence (vhdl model - synthesis) is of course a little bit "harder" than to implent it via fpga
http://www.ocf.berkeley.edu/~minar/dmp/vhdlAndScreenshots/data_sheets/Casc%20Integrator%20Comb%20Filter.pdf
However, Matlab has in its R14 a tool called filter hdl designer --> gererates automatically synthesiable code! and addittional a testbench. But if you want to design a filter optimized for low power and low area you should better design using your brain and hands. (typing your own code!!!).
I hope I could help you![/url]
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santhoshv78
Joined: 22 Jun 2004
Posts: 72
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| 08 Sep 2004 1:59 Re: sigma delta ADC |
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| How a complete layout of the modulator(1-bit) and also the decimator is done for the IC fabrication??
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eda4you
Joined: 17 Sep 2002
Posts: 283
Helped: 17
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| 08 Sep 2004 10:41 Re: sigma delta ADC |
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| santhoshv78 wrote: |
| How a complete layout of the modulator(1-bit) and also the decimator is done for the IC fabrication?? |
Hi,
the first design step s to have a SAM (system architectural model). This can be done for instance in matlab. With the results of this system simulation you are able to specify the order of the sigma-delta converter and the reurements for the analog building blocks. Afterwards the modulator and the deciamtor is designed. The decimator is usuall coded via hdl and synthezised and placed and routed using siliconensemble or design compiler for instance. The complited decimator block and the modulator are layouted manualy and a gdsii file is generated for the silicon foundary.
It's no problem to layout a placed&routed macro block, like a decimator, with analog blocks.
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xusoso
Joined: 18 Aug 2004
Posts: 90
Helped: 2
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| 08 Sep 2004 16:55 Re: sigma delta ADC |
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here is the Polyphase Decimation FIR Filter in verilog
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neocool
Joined: 03 Jun 2004
Posts: 79
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| 08 Sep 2004 20:41 Re: sigma delta ADC |
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| eda4you wrote: |
| However, Matlab has in its R14 a tool called filter hdl designer --> gererates automatically synthesiable code! and addittional a testbench. |
I have R13 version. Does it have some useful automatically generated synthesizable code tools?
I assume the update to R14 would cost some money...
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xusoso
Joined: 18 Aug 2004
Posts: 90
Helped: 2
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| 09 Sep 2004 10:38 Re: sigma delta ADC |
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maybe this article will give you help
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eda4you
Joined: 17 Sep 2002
Posts: 283
Helped: 17
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| 09 Sep 2004 12:10 Re: sigma delta ADC |
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| neocool wrote: |
| eda4you wrote: |
| However, Matlab has in its R14 a tool called filter hdl designer --> gererates automatically synthesiable code! and addittional a testbench. |
I have R13 version. Does it have some useful automatically generated synthesizable code tools?
I assume the update to R14 would cost some money... |
As I can remeber some thrid party prducts exist! But the functionality was very limited as I heard. Also R14 has a lot of incomplete functions. Not every filter can be hdl coded up to now.
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naomi
Joined: 04 Sep 2004
Posts: 9
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| 10 Sep 2004 14:51 Re: sigma delta ADC |
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thank you guys for the help..
i got lot of informationt with all of you guidence.
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kkoko
Joined: 07 Dec 2004
Posts: 22
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| 05 Jan 2005 18:47 Re: sigma delta ADC |
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| For this decimator you can read in one book DSP from Steve Smith
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