Rules | Recent posts | topic RSS | Search | Register  | Log in

How to design small reference Hi-speed Comparator

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> Analog IC Design & Layout
Author Message
andy2000a



Joined: 18 Jul 2001
Posts: 756
Helped: 7


Post20 Aug 2004 2:16   How to design small reference Hi-speed Comparator

In some power IC design need detect power mos Vds volt
and this volta is very small 20~30mv (Rds * current)
and who to design small volt comp ? becuase < 30mv
maybe OPA have large offset ..

and if I use series Comp hi-resolution but will low speed ..
Back to top
electronrancher



Joined: 24 Mar 2002
Posts: 479
Helped: 34


Post20 Aug 2004 6:43   How to design small reference Hi-speed Comparator

use pnp input stage to detect voltages close to ground, use pnp level shift + pnp input stages to detect voltage < GND.

Also, pnp will inherently have low offset. Keep gain low (20-50) in first stage, then offset of second stage does not matter - probably even cmos diff amp is ok.
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> Analog IC Design & Layout
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap