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Edward_2288
Joined: 07 Mar 2004
Posts: 72
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 18 Aug 2004 6:00 Inverter |
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hi, I dont know whether this topic should be put in digital or analog forum.
anyway, regarding to the inverter response, why do we want it to be symmetrical?
as a rule of thumb, generally, w/l for pmos is three time of that for nmos.
thx
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yjkwon57
Joined: 31 Jul 2004
Posts: 221
Helped: 21
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| 20 Aug 2004 20:34 Re: Inverter |
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| I think it is due to worrying about some unexpected timing violation. If one assure to meet the timing spec, then, it will be O.K. But, I would like to comment one thing: a slow changing input will cause the delay of the logic to be increased. Some unpopular EDA tools may not include this kind of timing models, some newbies may not be familiar with this kind of timing models, or no model values of this kind of timing models are not prepared to use.
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guamak_menanak
Joined: 13 Apr 2004
Posts: 139
Location: malaysia
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| 23 Aug 2004 5:32 Re: Inverter |
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nMOS use electron but pMOS used hole as a carrier. As you can see, electron is faster than hole, so we need bigger pMOS to make sure timing of the nMOS and pMOS is equal!
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electronrancher
Joined: 24 Mar 2002
Posts: 479
Helped: 34
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| 24 Aug 2004 5:01 Inverter |
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you want it to be symmetrical so that the threshold voltage (crossover voltage) of the inverter is equal to Vdd/2.
Now you have the most noise margin for process skew. Also makes timing nice since you know the big PMOS are as strong as the small NMOS, giving you symmetrical charge/discharge.
PS- this goes in digital forum not analog. See how noone knows the answer here? 
timing models? what? haha go read a book on digital, you got too far ahead of yourself.
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r23718
Joined: 01 Sep 2004
Posts: 6
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| 01 Sep 2004 8:01 Re: Inverter |
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| analog forum - not digital. Have you ever seen libraries those guys use? ANalog designer would be ashamed to use those....
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dumbfrog
Joined: 17 Jul 2004
Posts: 191
Helped: 4
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| 02 Sep 2004 5:04 Re: Inverter |
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 this topic is simple but belongs to this forum, just a personal opinion.
the trigger poin @ vdd/2 (somewhere between 2/1 to 3/1 ration) gives u more noise margin both for power drop and groundbounce, but it is not the fastest inverter. The tirgger point for fastest inverter is usually not vdd/2, but somewhere slightly lower than vdd/2.
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ykishore
Joined: 02 Sep 2004
Posts: 53
Location: india
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| 04 Sep 2004 12:51 Re: Inverter |
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The answer is only my oponion of the question posted but not read from any where. Hence if anybody finds faults with my answer you are free to post them in the forum.
My answer is :
Actually in the characteristics of an inverter there will be tolerance areas allowed in both the areas i.e., from transition from high to low and from low to high. These are called tolerance areas. Obviously it is nice to have both the tolerance areas i.e, for transition from high to low and from low to high equal the inverter characteristics are taken symmetric.
Pertaining to having posted this question here, My personal opinion is that this really belongs to both the digital and analog part. Hence, your confusion in posting it here is justified.
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