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danda821
Joined: 18 Jun 2002
Posts: 143
Helped: 2
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 06 Aug 2004 19:35 voltage controlled capacitor verilog a |
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| Does anyone know how to add a voltage-controlled cap in Cadence IC? I found a vccap model in analogLIb, but it can be only used in HspiceS. I want to use spectre simulator. Do I need to use Verilog-A or spectreHDL to model the device? Thank you.
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Hughes
Joined: 10 Jun 2003
Posts: 718
Helped: 87
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09 Aug 2004 5:23 vccap cadence |
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| With veriloga we can write more flexible models than hspice's vccap. I suggest you use veriloga.
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hanjiemy
Joined: 11 Jun 2004
Posts: 54
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09 Aug 2004 7:03 spice vccap |
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u can use Behavioral Cap in Hspice:
Cxxx net1 net2 "C=f(Vctrl)" TYPE=0,1,2
hope it can help u!
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DoctorX
Joined: 02 Sep 2004
Posts: 73
Location: USA
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15 Sep 2004 1:25 voltage controlled capacitor |
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| danda821 wrote: |
| Does anyone know how to add a voltage-controlled cap in Cadence IC? I found a vccap model in analogLIb, but it can be only used in HspiceS. I want to use spectre simulator. Do I need to use Verilog-A or spectreHDL to model the device? Thank you. |
You can just use a PMOS FET, hook the S and D to GND, and gate to the node desired. The substrate is your control handle. Apply a voltage to it. I know it works that way through two chips fabricated via MOSIS.
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nus_lin
Joined: 17 Feb 2005
Posts: 27
Helped: 1
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17 Feb 2005 8:09 voltage controlled capacitor in veriloga |
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| danda821 wrote: |
| Does anyone know how to add a voltage-controlled cap in Cadence IC? I found a vccap model in analogLIb, but it can be only used in HspiceS. I want to use spectre simulator. Do I need to use Verilog-A or spectreHDL to model the device? Thank you. |
did you solved this problem? if you have the modified model, can you share it with me?
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Vamsi Mocherla
Joined: 06 Sep 2004
Posts: 482
Helped: 62
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17 Feb 2005 8:52 cadence voltage controlled capacitor |
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| In the CDF model parameter form, you can enter a form for your cap with all the voltage coefficients. You refer to CDF parameter manual in Cadence
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nus_lin
Joined: 17 Feb 2005
Posts: 27
Helped: 1
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18 Feb 2005 4:34 cadence vccap |
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| Vamsi Mocherla wrote: |
| In the CDF model parameter form, you can enter a form for your cap with all the voltage coefficients. You refer to CDF parameter manual in Cadence |
actually the voltage controlled capacitor we are looking for is not a simple varactor.
the control voltage should be independant on the voltage applied to the capacitor. so it is a four terminal device.
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Vamsi Mocherla
Joined: 06 Sep 2004
Posts: 482
Helped: 62
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21 Feb 2005 8:22 cadence voltage controlled capacitance |
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| Then you can model a behavioural model using Verilog A with the cap value controlled by some other voltage
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ahmad_abdulghany
Joined: 12 Apr 2005
Posts: 1369
Helped: 212
Location: Cairo, Egypt
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02 Dec 2006 6:54 spectre model voltage controlled capacitor |
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try this:
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`include(disciplines)
module vari_cap( c_p, c_n, Vctrl_p, Vctrl_n);
electrical c_p, c_n, Vctrl_p, Vctrl_n;
parameter C, Co=1.0;
analog begin
C<+ Co*V(Vctrl_p,Vctrl_n);
I(c_p,c_n)<+ C*ddt(V(c_p,c_n));
end
endmodule
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And kindly tell me if it worked or even if it has some bugs (I just wrote it, but didn't run!!!)
Regards,
Ahmad,
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02 Dec 2006 6:54 Ads |
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timmy38
Joined: 11 Jul 2008
Posts: 1
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11 Jul 2008 16:26 voltage controlled cap model |
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Hi,
I tried to simulate it but there were some errors in the code, I tried to correct it but it didn't work.
I'm a beginner in Verilog A, could you please tell me how it works?
Thanks
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