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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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 06 Aug 2004 7:23 level shifting Techniques in cmos circuits |
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Does any body give me some info about the different level shifting techniques used in cmos circuit. I am interested in High speed level shifters. Any paper or pdf file is welcome.
Thanks.
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dumbfrog
Joined: 17 Jul 2004
Posts: 191
Helped: 4
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| 07 Aug 2004 15:12 Re: level shifting Techniques in cmos circuits |
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| for high speed logic level shift, low2high and high2low, the top performer is the simple differential latch type, up to 1GHz+ over PVT. if u want to level shift from hstl, sstl, or other analog signals, plese use an analog comparator. there are plenty of patents on levelshifter, just go to patent office website and do a search on level shifter.
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modern_analog
Joined: 11 Jul 2004
Posts: 9
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| 10 Aug 2004 0:51 Re: level shifting Techniques in cmos circuits |
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Can you be more specific.
Dumbfrog talked abt differential circuits
If yuo are doing single ended, what is the harm in just using a simple source follower. Of course, more distortion etc., but this will give you the best speed. Simplicity => speed
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 10 Aug 2004 6:13 Re: level shifting Techniques in cmos circuits |
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| modern_analog wrote: |
Can you be more specific.
Dumbfrog talked abt differential circuits
If yuo are doing single ended, what is the harm in just using a simple source follower. Of course, more distortion etc., but this will give you the best speed. Simplicity => speed |
can you give me scheme/details of this.
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goodboy_pl
Joined: 12 Mar 2002
Posts: 243
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| 10 Aug 2004 22:11 Re: level shifting Techniques in cmos circuits |
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I think u must be more specific about your application I know 3 type of level shifters:
1. in analog/continous ckts. like opamps, Some thing like source follower is used, they can be in isolated tub for more linearity but there is dangerous: instability or lower phase margin which means lower cut off frequency.
2. in DSM proceses, u need some method to shift low voltage signals of the core before sending them to the output and vice versa. in this case a differential crossed pair PMOS is conventional.
3. in power management HVICs with high side driver abilitym there is a need for high speed, high voltage, low loss and Common mode noise tolerant for ON/OFF signal shifting to the high voltage part of the IC; in this case differential pulse generators and RS flip-flop are used and are very conventional.
BEST!
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Colbhaidh
Joined: 10 Aug 2004
Posts: 151
Helped: 16
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| 11 Aug 2004 13:32 Re: level shifting Techniques in cmos circuits |
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| Are you reffering to IOs that are 3.3V down shifting to 1.8V for example?
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pantic
Joined: 06 May 2003
Posts: 93
Helped: 2
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| 12 Aug 2004 11:49 Re: level shifting Techniques in cmos circuits |
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| Quote: |
| Are you reffering to IOs that are 3.3V down shifting to 1.8V for example? |
I'm interested in those level shifters. Where can I get more information?
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dumbfrog
Joined: 17 Jul 2004
Posts: 191
Helped: 4
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| 13 Aug 2004 5:32 Re: level shifting Techniques in cmos circuits |
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| pantic wrote: |
| Quote: |
| Are you reffering to IOs that are 3.3V down shifting to 1.8V for example? |
I'm interested in those level shifters. Where can I get more information? |
u don't need a special levelshifter from 3.3V down to 1.8V
just connect the first inverter to 3.3V and the one that follow with 1.8V, you will get the 3.3V to 1.8V
(oops.....me bad....forgot to mention....both 3.3V and 1.8V inverter are 3.3V devices. ie 0.35um for both 3.3V and 1.8V inverter)
u only need a level shifter from low voltage to high voltage
Last edited by dumbfrog on 15 Aug 2004 21:07; edited 1 time in total |
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santhoshv78
Joined: 22 Jun 2004
Posts: 72
Helped: 1
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| 13 Aug 2004 7:31 Re: level shifting Techniques in cmos circuits |
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"
| Quote: |
u don't need a special levelshifter from 3.3V down to 1.8V
just connect the first inverter to 3.3V and the one that follow with 1.8V, you will get the 3.3V to 1.8V
u only need a level shifter from low voltage to high voltage" |
Why canot I do in viceversa..
Connect the first inverter to 1.8V and the second to 3.3V, assuming 3.3V MOSes are available..
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dumbfrog
Joined: 17 Jul 2004
Posts: 191
Helped: 4
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| 13 Aug 2004 16:40 Re: level shifting Techniques in cmos circuits |
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| santhoshv78 wrote: |
"
| Quote: |
u don't need a special levelshifter from 3.3V down to 1.8V
just connect the first inverter to 3.3V and the one that follow with 1.8V, you will get the 3.3V to 1.8V
u only need a level shifter from low voltage to high voltage" |
Why canot I do in viceversa..
Connect the first inverter to 1.8V and the second to 3.3V, assuming 3.3V MOSes are available.. |
In general, the spec for 3.3V standard's power supply range is from 3.0V to 3.6. The deisgner usually design the trigger point at 1/2 the supply voltage, 1.5V~1.8V. Do you think u have enough margin to turn the 3.3V stage on with 1.8V, the spec range from 1.65 to 1.95V for the 1.8V device.
Just a suggestion: please read the JDEC spec before u design anything.
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pantic
Joined: 06 May 2003
Posts: 93
Helped: 2
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| 15 Aug 2004 12:32 Re: level shifting Techniques in cmos circuits |
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| Quote: |
u don't need a special levelshifter from 3.3V down to 1.8V
just connect the first inverter to 3.3V and the one that follow with 1.8V, you will get the 3.3V to 1.8V
u only need a level shifter from low voltage to high voltage |
And what can I do if I don't have 1.8 V available? I mean, I want to obtain 1.8 V from a 3.3 V source. What can I do then?
Thanks
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Colbhaidh
Joined: 10 Aug 2004
Posts: 151
Helped: 16
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| 15 Aug 2004 16:59 Re: level shifting Techniques in cmos circuits |
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When shifting from 3.3V down to 1.8V you should not just connect the 3.3V invertor output to a 1.8V invertor input. The reason for this is the 1.8V circuitry uses thinner gate oxide which has a lower breakdown voltage and what is referred to as Charge to Breakdown. The oxide is guaranteed at the max of the 1.8V supply (typically +10%). The max of the 3.3V supply (typically 3.6V) would overstress the 1.8V input gates.
The best way to do this is use a hybrid low voltage invertor where there are two nmos pull down transistors which a 3.3V type gate oxides. These take the "out" and "(not)out" from the 3.3V invertor and pull down or not a pair of pmos 1.8V transistors (connected to 1.8V) connected as a latch.
This way guarantees no over stressing. I would attach a picture but have not worked out how to that yet !
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