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ncverilog problem

 
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gaonkc



Joined: 16 Jul 2004
Posts: 107
Post05 Aug 2004 8:43   ncverilog problem
I want to run many of vector for a chip in the test bench.
every time I only change the vectors used . But the compile time is more.
which way can be to reduce the run time.?
tnx
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