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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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 04 Aug 2004 10:10 circuit under pad |
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How the circuit under pad scheme is realized.
Is there any potential problems associated with this scheme.
This is related to I/Os circuits in cmos process.
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sunking
Joined: 25 May 2004
Posts: 914
Helped: 46
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| 05 Aug 2004 2:30 Re: circuit under pad |
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| As normal, the circuit under pad is power tr. or startup circuit
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rfsystem
Joined: 25 Feb 2002
Posts: 811
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| 05 Aug 2004 8:38 Re: circuit under pad |
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| Active circuits under pad-metal are forbidden because of mechanical stress at bonding time. That lead to too much yield loss.
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yorande
Joined: 19 Jan 2004
Posts: 101
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| 06 Aug 2004 5:30 Re: circuit under pad |
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| How about ESD circuit under pad?
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 06 Aug 2004 7:03 Re: circuit under pad |
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| I think TI & Motorola are using this concept for years to save silicon area.
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sunking
Joined: 25 May 2004
Posts: 914
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| 06 Aug 2004 8:02 Re: circuit under pad |
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| ESD can put under pad too,if it is a diode or bjt
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 06 Aug 2004 9:42 Re: circuit under pad |
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| I am worried about about the things which "sfsystem" has mentioned. So what actually done to counter those stressfull bonding events.
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ptoo30
Joined: 07 Apr 2002
Posts: 57
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| 06 Aug 2004 12:40 Re: circuit under pad |
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| i do not suggest to use active area nor ESD circuit beneath pad. i only know the register was located beneath it on 2 um rule for LCD panel driver. but deep sub-micron process causes huge mechanical stress, even register will have gig fluctuation of characteristics.
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 06 Aug 2004 12:53 Re: circuit under pad |
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| Do you have some information about the stress level which will be available to the circuit placed under pad.
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DoctorProf
Joined: 26 Mar 2002
Posts: 86
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| 06 Aug 2004 13:06 Re: circuit under pad |
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The process needs to be designed for ACTIVE AREA BONDING (AAB). This is the term used to describe puting circuitry under the bond pad. I work for a company that does this routinely in our internal processes. Many foundries do not allow this.
The mechanical stresses can be large but the failure typically is caused by mechnical fatigue of the oxide layers leading to cracks in the oxide under the pad. These cracks allow the various metal layers to short out.
The failures do not manifest themselves right away. Temperature cycling is the most effective way of stressing for this failure mechanism. We want our parts to pass electrically and not exhibit any cracks under the pad after 500 cycles from -65 to +150 C. If this occurs then we have a robust process.
I did a quick search on IEEE Xplore (http://ieeexplore.ieee.org/Xplore/DynWel.jsp) and found 85 articles on AAB (active <and> area <and> bonding).
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 06 Aug 2004 13:56 Re: circuit under pad |
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| So if I want to use this concept, I can use. Do I need to verify from the process people.
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DoctorProf
Joined: 26 Mar 2002
Posts: 86
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| 06 Aug 2004 14:43 Re: circuit under pad |
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| If the process allows it then there should be ground rules that determine how it can be used. I would check with the process guys or foundry to see if the process you are using allows AAB. If it does they should point you to the ground rules you need to follow to get reliable devices.
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sunking
Joined: 25 May 2004
Posts: 914
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| 09 Aug 2004 4:23 Re: circuit under pad |
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| http://www.edaboard.com/ftopic86262.html
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 09 Aug 2004 7:20 Re: circuit under pad |
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| DoctorProf wrote: |
| If the process allows it then there should be ground rules that determine how it can be used. I would check with the process guys or foundry to see if the process you are using allows AAB. If it does they should point you to the ground rules you need to follow to get reliable devices. |
I am using 90nm TSMC process.
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staric
Joined: 26 Sep 2003
Posts: 79
Helped: 1
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| 09 Aug 2004 15:20 circuit under pad |
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| There are many ESD device be designed under the pads I saw. I think it can save area. Most of these ESD device are diode ESD.
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Nobody
Joined: 04 Oct 2001
Posts: 250
Location: Formosa
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| 09 Aug 2004 17:14 circuit under pad |
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| as i know , there is one set of circuit under pad library from SMIC 0.18um . However no mass production data available for reference . So far it show sucessful under shuttle verification . Need for futher investigation about the reliability .
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sunking
Joined: 25 May 2004
Posts: 914
Helped: 46
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| 10 Aug 2004 3:52 Re: circuit under pad |
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There are many kind of product has device under pad. such esd, startup circuit, body Res. and so on.
It is important that the device which is under pad is body device.
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jimjim2k
Joined: 17 May 2001
Posts: 1243
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| 10 Aug 2004 8:11 Re: circuit under pad |
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Hi
Look at this url for pad frames and more.
1. h**p://www.ece.iit.edu/~vlsi/cadence/pads/
A good tutorial on using cadence Tools (recommended)
2. h**p://www.ece.iit.edu/~vlsi/cadence/
* -> t
tnx
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andy2000a
Joined: 18 Jul 2001
Posts: 756
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| 10 Aug 2004 9:19 Re: circuit under pad |
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I have one question .. I friend use umc 0.18um process
and put some CKT under PAD ..
then --> pad have pad_pilling problem .,,
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 10 Aug 2004 9:25 Re: circuit under pad |
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| andy2000a wrote: |
I have one question .. I friend use umc 0.18um process
and put some CKT under PAD ..
then --> pad have pad_pilling problem .,, |
Is this some kind of DRC problems. Like I have seen that few of the DRC tech. files have some rules that does no allow any active circuit to be placed under the PAD.
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Colbhaidh
Joined: 10 Aug 2004
Posts: 151
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| 10 Aug 2004 11:49 Re: circuit under pad |
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There can be process related issues to circuits beneath the bond pad. Typically in IC processing, there is a hyrogen anneal step to de-activate any "dangling bonds" in the cmos gate areas. Beneath the Bond Pad metal in modern technologies will be a Titanium Nitride and Titanium layer. This layer will stop hydrogen passing through. This would only really be an issue for circuits beneath the pad that need strick control over threshold voltage or where matching is a concern.
State of the art ultrasonic bonding should not be an issue with stress beneath the pads which is why TSMC and Chartered Semi allow some circuitry beneath the pads. I am surprised that UMC does not at 0.18um node.
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electronrancher
Joined: 24 Mar 2002
Posts: 479
Helped: 34
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| 20 Aug 2004 6:59 circuit under pad |
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no no no! i disagree 100% with AAB
i saw horrible failures when some idiot tried to use AAB on his power mosfet. breakdown voltage was reduced by almost 80%, hot carrier wearout was much easier, all in all it was junk. the gates were crushed, the thin oxide (150A/0.6um process) was often cracked, the cross sections looked like hell!
i might put pn junctions under my bondpad, but NEVER gate or gateox. it might work for your experimental ceramic chips, using soft gold bondwire, hand bonded by someone who knows what they're doing... but in offshore production, bashing aluminum bondwires on at a rate of 10/second - your structures will be crushed, i promise you.
i know for a fact that carsem (actually a pretty good assembly house) could break the bondpads right out of any chip without barrier metal. even then the ILD thickness had to be increased to act as a shock absorber - and you want to put gateox under this? you should be wondering if your silicon itself is going to break!! 
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 26 Aug 2004 14:53 Re: circuit under pad |
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| electronrancher wrote: |
no no no! i disagree 100% with AAB
i saw horrible failures when some idiot tried to use AAB on his power mosfet. breakdown voltage was reduced by almost 80%, hot carrier wearout was much easier, all in all it was junk. the gates were crushed, the thin oxide (150A/0.6um process) was often cracked, the cross sections looked like hell!
i might put pn junctions under my bondpad, but NEVER gate or gateox. it might work for your experimental ceramic chips, using soft gold bondwire, hand bonded by someone who knows what they're doing... but in offshore production, bashing aluminum bondwires on at a rate of 10/second - your structures will be crushed, i promise you.
i know for a fact that carsem (actually a pretty good assembly house) could break the bondpads right out of any chip without barrier metal. even then the ILD thickness had to be increased to act as a shock absorber - and you want to put gateox under this? you should be wondering if your silicon itself is going to break!! |
If we use differrent type of dielectric / Mess sturcture of metal in PAD to relieve. Then it can be possible to use active device under PAD.
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electronrancher
Joined: 24 Mar 2002
Posts: 479
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| 26 Aug 2004 16:09 Re: circuit under pad |
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i don't think you need to use quote if our posts are right next to each other!
anyway, i was just offering my opinion - i know of several dielectrics that don't work, but none that do. if you have success, please post it here - i'd be interested to see your results.
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harveyg
Joined: 26 Aug 2004
Posts: 4
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| 26 Aug 2004 17:24 Re: circuit under pad |
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I have never tried this but am considering it. Surely the key to success here is to treat it as a mechanical engineering problem. Likely its possible to create metal/via layouts which concentrate stress and others that equalize stress or perhaps still further ones that direct stress away from thin oxide.
So isn't it possible that for a carefully designed hand layout (like ESD) this might work without significant yield impact.
Meanwhile automatic place and route circuitry on the same process might not be successful because hidden in the jumble it creates is a stress concentrator over a fragile structure.
Any thoughts?
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electronrancher
Joined: 24 Mar 2002
Posts: 479
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| 27 Aug 2004 1:30 Re: circuit under pad |
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the risk for diffused structures is low, but cmos i feel is a bad candidate for under-pad.
maybe probe pad if it's not going to be bonded. but these are few.
if anyone has cross-sections of a die with cmos gates under a pad that have survived, i would like to take a look at the ILD structre.
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harveyg
Joined: 26 Aug 2004
Posts: 4
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| 27 Aug 2004 10:12 Re: circuit under pad |
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What I am considering is a large area of thin oxide capacitance - so it could be made essentially featureless under the bond area.
I would be interested to know, did the the ILDs you have seen 'not work' fail around some under (or over) lying feature specifically?
(Intuitively even quite fragile materials can support considerable loads when sandwiched between tougher and conformal surfaces.)
Interested to know you thoughts.
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harveyg
Joined: 26 Aug 2004
Posts: 4
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| 14 Sep 2004 10:27 Re: circuit under pad |
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See paragraph 3 of article below
http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=47204387
Kulicke & Soffa releases gold bonding wire technology
Silicon Strategies
09/13/2004, 10:05 AM ET
WILLOW GROVE, Pa. — Kulicke & Soffa Industries Inc. has released a new gold bonding wire technology for advanced wirebonding applications.
Called Radix, the wire has a higher intermetallic stability for improved reliability, according to the company. Radix bonding wire has shown superior reliability on a wide range of aluminum bond pad compositions and thicknesses, the company said.
The new bonding wire lowers hardness on free-air balls (FAB), which allows for bonding on sensitive devices structures like low-k dielectrics and bonding over active circuitry, it added.
"Many of our global customers have been asking for higher reliability without compromising lower electrical resistivity," said Ilan Hadar, K&S' vice president of bonding materials. "Radix wire gives customers the best of both worlds."
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Colbhaidh
Joined: 10 Aug 2004
Posts: 151
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| 15 Sep 2004 13:40 Re: circuit under pad |
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Typically for each layer of metal there is at least 0.8um of TEOS or similar oxide, and roughly 0.8 to 1um between Si at the 1st metal layer.
If you are using < 3 layers of metal, I would agree not to using circuitry under the pads. but for >3LM there will not be any significant stresses from the bonding at the transistor level. If there is, then there is a serious problem with the assembly site. I have been in IC processsing for > 20 years and never experienced assembly problems like that of CARSEM. (I have heard of problems with that particular company though ..).
Typical bonding pads are connected to underlying metal through a sea of tungsten plugs (sometimes, but not necessarily, directly beneath the bond - something I would not advise.) Tungsten is very hard compared to the oxide so if the ultrasonic weld moved the top layer metal sufficiently, it would fix the oxide between the plugs. This would be a severe reliability hazard and would fail the assembly house qualification if it existed.
I have seen active circuitry beneath tyhe pads on 5LM and 6LM at 0.18um and 0.13um with no issues (except matching mentioned above).
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Teddy
Joined: 15 Sep 2004
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| 16 Sep 2004 22:36 Re: circuit under pad |
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I used circuit under pad before and will use it again.
Some foundries do not like it but you can surely have a waiver for that.
In our case it has to go through reliability testing and assembly site has to agree with that. In general technology guys do not have to care (especially when you use 3+ metal layers).
In old dayes they were putting N- / P- well under pad in case the wire would go "through" pad metal - but did not see it when 2+ metals arrived.
I would try it - with note to management that there could be some issues.
ESD? sure - active = "core" circuitry no thanks
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