One of our Clients, a US-based Company, has the following requirement for their Bangalore operations:
Design Methodology Engineer
1. Experience in RTL synthesis and simulation using VHDL and Verilog, memory interfacing and memory architecture.
2. System Design using FPGA devices from Xilinx and/or @ltera
3. System modeling experience using high-level languages such as C, C++, or SystemC.
4. Familiarity with multimedia or wireless domain
5. Good communication skills
6. BSEE required. A Masters would be advantageous
7. Experience of 3-6 years
Candidates meeting these requirements may send in their latest resume’ to hr(at)polycorps.com, mentioning “PCS/PS247/EMJ” in the subject line.
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