| Author |
Message |
Sunrising
Joined: 10 May 2004
Posts: 14
|
 29 Jul 2004 1:49 Incorrect leakage of spice model |
|
|
|
|
If a spice model gives out incorrect leakage for VGS=VSB=0 and VDS=VDDMAX,
How to change the spice model to reduce this leakage?
What are the parameters critical to this leakage?
|
|
| Back to top |
|
 |
dumbfrog
Joined: 17 Jul 2004
Posts: 191
Helped: 4
|
| 29 Jul 2004 6:24 Re: Incorrect leakage of spice model |
|
|
|
|
don't know about your technology spice model
for tsmc, there is a leakage model (ie. pmos_g/nmos_g) for leakage simulation.
|
|
| Back to top |
|
|
maxwellequ
Joined: 27 Jun 2001
Posts: 185
Helped: 11
|
| 29 Jul 2004 23:55 Re: Incorrect leakage of spice model |
|
|
|
|
What do you mean by "leakage"? Gate Current (I think - not sure - that this is what dumbfrog is referring to )? Drain current with VGS=0 (yes it exists and it can be somehow large in the most recent technologies...) ?
Can you tell us what is the model that you are using ? Did you obtain it from the foundry ? How do you know it is wrong ?
|
|
| Back to top |
|
|
Sunrising
Joined: 10 May 2004
Posts: 14
|
| 30 Jul 2004 3:31 Re: Incorrect leakage of spice model |
|
|
|
|
1. Leakage there is Ioff as indicated by VGS=VBS=0 and VDS=VDDMAX.
2. Our spice model is from GRACE, no leakage model available
3. The circuit is a bandgap with just 0.8uA current. Typical Ioff should be in the order of 1pA~1nA/um. Large leakage at high temperature will destroy the normal operation of bandgap.
Any suggestions are welcome. Thanks in advance.
|
|
| Back to top |
|
|
rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
|
| 30 Jul 2004 9:26 Re: Incorrect leakage of spice model |
|
|
|
|
When VGS = VSB = OV & VDS= VDDMAX. Then the primary leakage current component are
1) reverse saturation current between drain & substrate.
2) sub threshold current between drain & sourse voltage (this is called Ioff). This is dependent on the lenght of the MOS. so if you want this to be less then increase your L.
So do you want to modify your MOS models for decreasing this curren then go to your MOS model's file, search for ioff term & modify it.
|
|
| Back to top |
|
|
maxwellequ
Joined: 27 Jun 2001
Posts: 185
Helped: 11
|
| 30 Jul 2004 13:47 Re: Incorrect leakage of spice model |
|
|
|
|
The standard MOS models used in industry (BSIM3 or BSIM4 series) model that drain current, which EXISTS for VGS=0 and VDS>0. Other older MOS models may do a very bad job in modeling this. So, first confirm what is the model that you are using.
You should only try to modify the model IF YOU ARE SHURE IT IS WRONG. In principle you should trust the model given by the foundry.... When changing the model you may get nice simulation results that may not exist in reality...
As it was already mentioned by rajesh13 this current is composed by two terms:
1) The reverse saturation current between drain and substrate - depends on the area and perimeter of the drain diffusion. You can only decrease it by decreasing the W of the transistor.
2) The subthreshold current between drain and source - probably this is the one you are having problems with. To decrease it you must increase L - also increasing W if you want to maintain the W/L ratio. If you can afford it, leave the W as small as possible.
In some technologies there are several "flavors" of transistors, for the same max operating voltage, which basically differ in their Vt’s. If this is the case, use a transistor with a higher Vt.
|
|
| Back to top |
|
|
yjkwon57
Joined: 31 Jul 2004
Posts: 221
Helped: 21
|
| 01 Aug 2004 23:59 Re: Incorrect leakage of spice model |
|
|
|
|
Hi.
I think there is no leakage model practically used in the EDA tools. The leakage current is different from the reverse saturation current and is usually much much higher than the reverse saturation current. The leakage is caused by some traps in the depletion layer, which act as the recombination centers. Good wafers will have less traps in them.
Bye~~~
|
|
| Back to top |
|
|
rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
|
| 02 Aug 2004 8:17 Re: Incorrect leakage of spice model |
|
|
|
|
| maxwellequ wrote: |
The standard MOS models used in industry (BSIM3 or BSIM4 series) model that drain current, which EXISTS for VGS=0 and VDS>0. Other older MOS models may do a very bad job in modeling this. So, first confirm what is the model that you are using.
You should only try to modify the model IF YOU ARE SHURE IT IS WRONG. In principle you should trust the model given by the foundry.... When changing the model you may get nice simulation results that may not exist in reality...
As it was already mentioned by rajesh13 this current is composed by two terms:
1) The reverse saturation current between drain and substrate - depends on the area and perimeter of the drain diffusion. You can only decrease it by decreasing the W of the transistor.
2) The subthreshold current between drain and source - probably this is the one you are having problems with. To decrease it you must increase L - also increasing W if you want to maintain the W/L ratio. If you can afford it, leave the W as small as possible.
In some technologies there are several "flavors" of transistors, for the same max operating voltage, which basically differ in their Vt’s. If this is the case, use a transistor with a higher Vt. |
I have a opinion about the modelling of leakage currents in MOS.
Like the modelling team does not model this properly & correctly as I have found out several times that the leakage currents values which I get with CAD (simulations) is always much less then the actual silicon values.
|
|
| Back to top |
|
|
