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arizona999
Joined: 25 Jul 2003
Posts: 28
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 22 Jul 2004 5:59 Problem of LVS |
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tried to use LVS function in c(at)dence, but did not get through.
The error is as if I can not create the netlisting file from extracted and schematics:
Running artist flat netlisting ...
Warning: Invalid cell view - 0(unknown)
did any body have this problem before? Please tell me how to solve it.
Thanks a lot.
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flyankh
Joined: 16 Feb 2004
Posts: 94
Helped: 2
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| 22 Jul 2004 7:31 Problem of LVS |
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| Why not use DRACULA or other tools?It's a more professional tools than Cadence in LVS.
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Serg_SV
Joined: 30 Jun 2004
Posts: 67
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| 22 Jul 2004 12:09 Problem of LVS |
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| Dracula? Who producer does this soft?
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shiowjyh
Joined: 29 May 2003
Posts: 114
Helped: 1
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| 23 Jul 2004 8:29 Re: Problem of LVS |
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Guys,
DRACULA is the one you are doing LVS in C(at)dence... 
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flyankh
Joined: 16 Feb 2004
Posts: 94
Helped: 2
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| 23 Jul 2004 8:40 Problem of LVS |
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Don't cry,It's my fault.
arizona,have you done it?
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arizona999
Joined: 25 Jul 2003
Posts: 28
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| 24 Jul 2004 6:10 Re: Problem of LVS |
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| flyankh wrote: |
Don't cry,It's my fault.
arizona,have you done it? |
Thanks a lot.
No, I have not solved this problem yet. I just wonder if it is the c(at)dence configuration problem or my fault.
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Hughes
Joined: 10 Jun 2003
Posts: 715
Helped: 85
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| 28 Jul 2004 10:20 Problem of LVS |
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| Are you using divaLVS tools? Did you check the CDS_Netlisting_Mode environment variable?
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piao
Joined: 12 Feb 2003
Posts: 223
Helped: 7
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| 28 Jul 2004 15:00 Problem of LVS |
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If you use divaLVS, do you have the ivpcell or auLVS and some other cell view for LVS in your corresponding pmos nmos views, there should not only a pmos/nmos symbol and spectre . spice views.
If you generate analog/digital netlist, you should set the CDS_Netlisting_Mode to generate m= or m is not effective.
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rajesh13
Joined: 07 Jul 2004
Posts: 126
Location: Milky Way
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| 02 Aug 2004 10:06 Re: Problem of LVS |
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| please check .simrc file in your area. I think you have not listed the view name whose netlist you want to produce.
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arizona999
Joined: 25 Jul 2003
Posts: 28
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| 21 Aug 2004 8:48 Problem of LVS |
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I use layoutPlus to do the layout, I do not know if it is Dracula or davaLVS, who can tell me who to check it out? I am a new learner in this area.
Thanks a lot.
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Hughes
Joined: 10 Jun 2003
Posts: 715
Helped: 85
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| 22 Aug 2004 23:59 Problem of LVS |
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Verification tool is different from layout tool. Dracula can run standalone with a GDSII input.
If you are using "Verify / Extract..." and "Verify / LVS..." menus to do LVS, you are using diva.
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Question
Joined: 11 Aug 2004
Posts: 76
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| 24 Aug 2004 10:46 Problem of LVS |
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| I can tell you a method, but I am not sure it is useful. First, you simulate your schmatic by spectre. Then change simulater to hspiceS, and ceate a netlist. Then change back the simulater to spectre, and receate the netlist. After do it, you can run your LVS again. good luck!!
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dragonwell
Joined: 31 Mar 2004
Posts: 28
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| 01 Sep 2004 12:28 Re: Problem of LVS |
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I used to have the similar problem. Have set the env variable "CDS_Netlisting_Mode=Analog" already solved the problem. If you are running digital design, set the mode to Digital.
Hopefully can help a little.
Good luck!
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Hughes
Joined: 10 Jun 2003
Posts: 715
Helped: 85
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| 01 Sep 2004 14:36 Problem of LVS |
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| The words "analog" and "digital" sometimes are confused in terms of divaLVS. In fact, CDS_Netlisting_Mode should be set to Analog if the schematic is built with library analogLib. It should be set to Digital or null string if library sample is used rather than analogLib.
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DoctorX
Joined: 02 Sep 2004
Posts: 73
Location: USA
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| 03 Sep 2004 22:37 Re: Problem of LVS |
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You should first identify to us what "Design Kit" you are using. If you are from university, I assume that you have either NCSU CDK or Cadence PDK. For NCSU CDK, before you get LVS, you should do:
1. run Verify/DRC in Virtuoso. Make sure it is violationfree. Otherwise it won't extract sometimes.
2. Run Extraction.
3. Run LVS. Make sure it is "Schematic against Extracted view", not Schematic against Layout, which is a common mistake. There is no circuit information in Layout view.
For NCSU CDK, three files are essential: divaEXT.rul, divaLVS.rul, divaDRC.rul, all under /local/techfile/. The rule files (if you have not tweaked them) are supposed to be applicable for all technologies, which is of course impossible. Tell me about your design kit, technology, or even tar me your design or a sample design by email, and I can look it over for you.
| arizona999 wrote: |
tried to use LVS function in c(at)dence, but did not get through.
The error is as if I can not create the netlisting file from extracted and schematics:
Running artist flat netlisting ...
Warning: Invalid cell view - 0(unknown)
did any body have this problem before? Please tell me how to solve it.
Thanks a lot. |
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zx2051
Joined: 23 Oct 2003
Posts: 20
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| 07 Sep 2004 14:09 Problem of LVS |
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| use dracula ,it is good
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Question
Joined: 11 Aug 2004
Posts: 76
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| 09 Sep 2004 2:50 Re: Problem of LVS |
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| piao wrote: |
If you use divaLVS, do you have the ivpcell or auLVS and some other cell view for LVS in your corresponding pmos nmos views, there should not only a pmos/nmos symbol and spectre . spice views.
If you generate analog/digital netlist, you should set the CDS_Netlisting_Mode to generate m= or m is not effective. |
OK, I know it. It is the problem, thanks.
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Teddy
Joined: 15 Sep 2004
Posts: 281
Helped: 38
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| 16 Sep 2004 23:01 Re: Problem of LVS |
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| Well I guess it is about year too late but check the view list and a stop view
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