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suraj
Joined: 20 Jul 2004
Posts: 17
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 20 Jul 2004 19:57 Low Volatge Analog IC. |
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Hello Friends,
I have very basic questions about the Low volatge Analog IC.
1. Why we go for Low Votage Analog Design and its benifits and drawbacks.
2. What are the Challenges we face when we low volatge Analog circuits.
3. Suggest me some papers which explains Low Voltage Analog Design techniques.
Thanks a lot for your help.
Suraj
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rfsystem
Joined: 25 Feb 2002
Posts: 811
Helped: 88
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| 20 Jul 2004 22:52 Re: Low Volatge Analog IC. |
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Because of cost reasons!
If only <25% is analog which does not shrink the shrink of the digital gives cost advantage. So analog have to go down the path with the digital logic. Mixed voltage and oxide thickness delay this process a little bit. But voltage headroom goes down. So at the same time current should go up. Vertical device stacking end at one device. So the analog performance would go down to the point where it could not further compensated by the digital part. Then system level partioning enters the field which have mixed technologies. That would allow the best cost situation in furtuere I expect. That is at about the point where analog processes allow enough digital to make compensation and configuration of the anlog cost effective. Then raw digital is done at 1V and less.
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hrkhari
Joined: 04 Mar 2004
Posts: 225
Helped: 3
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| 21 Jul 2004 4:17 Re: Low Voltage Analog IC. |
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Hi Suraj:
From the point of High frequency analog circuit design, the answers to your questions are:
1.Low voltage architectures is necessary to increase the Life time perweight of the battery used in PDA’s
2.Obtaining high dynamic range output, with reduced stacked transistors hence proposing novel architectures serves as the main challenge in realizing this architectures.
3.You could browse through this papers for more information:
Manku, T., Beck, G. & Shin, E.J. (1998). A Low-Voltage Design Technique for RF Integrated Circuits. IEEE Transactions on Circuits and System II: Analog and Digital Signal Processing, 45(10), 1408-1413.
Svelto, F., Conta, M., Torre, V.D. & Castello, R. (1999). A Low Voltage Topology for CMOS RF Mixers. IEEE Transactions on Consumer Electronics, 45(2), 299-309.
MacEachern, L.A.& Manku, T.(1999). A Low Voltage and Low Power Integrated Radio Frequency Mixer. Proceedings of the 1999 IEEE Canadian Conference on Electrical and Computer Engineering, 525-528.
Rgds
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v_naren
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| 22 Aug 2004 7:50 Re: Low Volatge Analog IC. |
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1) The channel length is dropping due to digital guys...The maximum voltage which can ever be applied across the D and S of the FET is also dropping, to prevent electric breakdown of the material due to high electric fields....E =V/L as L decreasing => E increasing...thus to maintain E low enuf the V is also decreasing => VDD is decreasing thus the VDD is 1.8V and so on...now hence the traditional analog circuits like telescopic opamps and cascode based LNAs and all just plain dont work.,....so we ANALOG GUYS DONT WANT TO GO FOR LOW VOLTAGE BUT RATHER ARE BEING FORCED TO GO...CORRECTION TO UR QUESTION HERE
2) like in point1 since the maximum voltage swing is limited thus the architectures to be used are only folded cascode as an example...but please not the that the DC power consumed will be two times higher....  ..anyway so if we still use telescopic based config for our amps then the signal swing is terribly limited...but if we use folded then DC power consumed is too large...so analog guys cannot go wither way...thus there is a tradeoff between swing, breakdown, power dissipated and actually even noise is involved..that I will not go into much
3) go and search
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sunking
Joined: 25 May 2004
Posts: 914
Helped: 46
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| 26 Aug 2004 7:30 Re: Low Volatge Analog IC. |
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| the reason is cost and speed.
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guamak_menanak
Joined: 13 Apr 2004
Posts: 139
Location: malaysia
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| 27 Aug 2004 2:58 Re: Low Volatge Analog IC. |
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2) like in point1 since the maximum voltage swing is limited thus the architectures to be used are only folded cascode as an example...but please not the that the DC power consumed will be two times higher.... ..anyway so if we still use telescopic based config for our amps then the signal swing is terribly limited...but if we use folded then DC power consumed is too large...so analog guys cannot go wither way...thus there is a tradeoff between swing, breakdown, power dissipated and actually even noise is involved..that I will not go into much
why the DC power consumtion become 2x higher?
can someone explain?
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v_naren
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| 27 Aug 2004 4:09 Re: Low Volatge Analog IC. |
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ok...remember the folded cascode structure?
In a telescopic cascode the current flowing thru both MOSFETs is the same. and hence the power dissipated will be VDD*IBIAS
In a folded cascode, please see Fig 6.26 in analysis and design of analog ICs by gray and meyer, u can observe that the bias current will need to supply drain currents of the two transistors. In general we set the bias currents thru both transistors same so that the small signal analysis remains same as in case of telescopic cascode. Thus then the total current drained will be 2IBIAS. thus power cosumed will be 2*VDD*IBIAS.
Hence the power consumed is mostly 2times.
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terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
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| 28 Aug 2004 12:07 Re: Low Volatge Analog IC. |
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For the low voltage Analog IC, I also thing that it is forced by digital part that analog guys are going to use some special low-voltage technique such as switched-opamp or reset opamps and also two-stage opamp to solve the problems of switches and output swings.
Actually this is due to the continuing decreasing feature size of transistors as benefits to digital circuits. However, I have heard some other guys have different comments on low-voltage circuits as follows:
" Actually developing low-voltage analog techniques is not so mandatory as many people thinks. For examples, in 90 nm technology which limit the maximum supply voltage to around 1.2V (not quite sure, I just want to give an example), the Vth for PMOS and NMOS is around 0.2-0.3V, so for Vcm = 0.6V and reasonable output swing of 1Vp-p differential, the floating switches does not post problem as they still can turn on. Thus switched opamp or reset opamps techniques for low-voltage analog circuits is not as necessary but only to place severe trade off in power, speed, noise, etc....." I think one of the example can be found in one of the ISSCC 2004 paper about 1.2V 10-bit pipelined ADC working at 220MHz.
Do anyone have some comments on this? I really hope to knows what actually people keep in minds about low-voltage issues.
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layes
Joined: 27 Sep 2004
Posts: 57
Helped: 2
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| 09 Oct 2004 5:54 Re: Low Volatge Analog IC. |
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1,low power
2,voltage swing and vth
3,cmfb
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Bin_Wang
Joined: 07 Mar 2004
Posts: 16
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| 09 Oct 2004 6:23 Re: Low Volatge Analog IC. |
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a book is recommend about low voltage analog IC
"low voltage /low power integrated circuits and system low voltage mixed-signal circuits"
edit by Edgar Sanchez-Sinencio
1.low voltage can make the IC low power and can run with battery power supply in portable device
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layes
Joined: 27 Sep 2004
Posts: 57
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| 11 Oct 2004 5:19 Re: Low Volatge Analog IC. |
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sc resistence
in the middle will huge
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rtpq
Joined: 12 Oct 2004
Posts: 15
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| 12 Oct 2004 12:13 Re: Low Volatge Analog IC. |
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| Adding to current consumption increase, I think more area is needed to realize low voltage requirement like rail-to-rail and uniformized gain.
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