justin
Joined: 02 Jun 2004
Posts: 20
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 15 Jul 2004 12:25 How to import the edif file to the cadence from the DA? |
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I design a mixed circuit, and I want to simulate it through s*nopsys design analyzer and cadence. I design digital part in verilog, and then synthesize it in DA, and save it as edif file. When I want to import it into cadence, I failed. I in fact want to simulate in hspice.How can I do? Is the method possible?
When I save it as verilog file after synthesized, failed again.
I just want to simulate in this form, because the main part is in analog.
Can spectre perform this? How to do?
thanks
Best Regards
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