14 Jul 2004 14:35 Is history effect of SOI a trouble maker in circuit designs?
Based upon the characteristics of floating body in SOI, history effect seems to be a trouble maker in circuit designs and simulations. Does it seriously impact on the circuit performance?
14 Jul 2004 15:17 Re: Is history effect of SOI a trouble maker in circuit desi
One of the biggest. You could simulate your regular working analog CMOS circuit is you modify each
bulk. For PMOS and for NMOS make an additional series RC network. That mimic the floating body. But
negleate the intercoupling. So you now that about 20-30% of the gate charge is put into substrate.
Now also the sereis RC network react by controlling the backgate by about 30%. So analog design with
floating bodies is a complete new jungle to learn and live with.
