| Author |
Message |
terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
|
 09 Jul 2004 4:49 corner analysis of Vth |
|
|
|
|
| Do anyone has some experience on how the threshold voltage of MOSFET varies with different corner cases? I have simulated a source follower to perform a level shift in corner analysis, but I found that the Vth variations can be as large as 300-400 mV. Is it normal or not? How can we achieved accurate level shift with such large variations? (amount of level shift = Vgs = Vth+Vov where Vov is mainly fixed by current)
|
|
| Back to top |
|
 |
uladz55
Joined: 11 Mar 2004
Posts: 161
Helped: 6
|
| 09 Jul 2004 8:15 Re: corner analysis of Vth |
|
|
|
|
For TSMC 0.5u process VTO variation for corner is +/- 120mV.
For TSMC 0.35u - +/- 100mV (Vcc=3V).
But actually deviations are smaller.
|
|
| Back to top |
|
|
terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
|
| 09 Jul 2004 16:33 Re: corner analysis of Vth |
|
|
|
|
| That means your VGS can have also such large variations. So how can one design level shifter using source follower with such large VGS variations?
|
|
| Back to top |
|
|
electronrancher
Joined: 24 Mar 2002
Posts: 479
Helped: 34
|
| 10 Jul 2004 7:38 corner analysis of Vth |
|
|
|
|
mostly, if your vth falls it's due to thin oxide and it means both NMOS and PMOS are affected. now even though your level shift has lower vgs and lower level shift, you other thresholds shift and track it.
what you're trying to do is called design margining. as a given parameter varies, how can you balance the input and output in order to cancel it as much as possible.
In this case, you're saved by the fact that Vth usually tracks well between NMOS and PMOS. In fact, I almost never see skews between NMOS and PMOS, and in my opinion is a sign your fab is not in control.
You should margin using your ff/ss cases, and in case something is falling apart and you can't tell what, use the skew cases (fs or sf) to tell you whether NMOS or PMOS is the culprit.
|
|
| Back to top |
|
|
terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
|
| 10 Jul 2004 11:52 Re: corner analysis of Vth |
|
|
|
|
| That's means that sf/fs case is seldom appeared in real chips?
|
|
| Back to top |
|
|
mazelk
Joined: 23 Apr 2004
Posts: 107
Helped: 2
Location: COLOMBIA
|
| 10 Jul 2004 13:37 Re: corner analysis of Vth |
|
|
|
|
Greetings....
If you are design a source follower (common drain), you must put attention to body effect. This efect consists in a shift of threshold voltage, according to voltage between source and body (substrate). You may avoid it, putting this source at the least voltage in circuit (e.g: common source).
Mathematically:
Vth=Vt0+gamma*(sqrt(2*phi+Vsb)-sqrt(2*phi))
|
|
| Back to top |
|
|
electronrancher
Joined: 24 Mar 2002
Posts: 479
Helped: 34
|
| 12 Jul 2004 0:03 Re: corner analysis of Vth |
|
|
|
|
do not disregard the sf/fs cases, as they will tell you which variety of transistor is causing the most variation in your circuit performance, but yes, skew cases (of that extreme) are uncommon in production.
yes, you should expect some skew between your NMOS and PMOS as the body of each is a different well, but usually the variance in skew is small compared to the overall fast/slow trend.
think of the n-well process. substrate doping varies quite a bit. n-well doping varies less, but still is significant. s/d implants are usually better controlled, threshold adjust is about the same as s/d implant, and gate oxide thickness varies depending on fab - some are very good, some have lots of variation.
substrate doping affects both NMOS & PMOS in a trend, where as n-well only affects PMOS - one source of skew. s/d implant may cause rds skew but not Vt, threshold adjust affects both at the same time, and finally tox skews both at the same time.
now you can see it would be odd to have high threshold on one device and low threshold on the other - most CMOS processes are pretty resistant to that.
|
|
| Back to top |
|
|
RC13
Joined: 24 Apr 2002
Posts: 122
|
| 12 Jul 2004 9:36 Re: corner analysis of Vth |
|
|
|
|
| terryssw wrote: |
| Do anyone has some experience on how the threshold voltage of MOSFET varies with different corner cases? I have simulated a source follower to perform a level shift in corner analysis, but I found that the Vth variations can be as large as 300-400 mV. Is it normal or not? How can we achieved accurate level shift with such large variations? (amount of level shift = Vgs = Vth+Vov where Vov is mainly fixed by current) |
-don't expect level shifter to have absolute shifting
-you haven't choosen the right sizing of your level shifter.
|
|
| Back to top |
|
|
terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
|
| 13 Jul 2004 5:36 Re: corner analysis of Vth |
|
|
|
|
| Thanks very much for all of your replys. I have one more questions in corner simulation is, usually how much margins (in mV) do you leaved to ensure the MOSFET in saturation region in terms of Vgs-Vth and Vds-Vdsat under typical and worst case corner situations? Is it difference required margins for PMOS and NMOS?
|
|
| Back to top |
|
|
electronrancher
Joined: 24 Mar 2002
Posts: 479
Helped: 34
|
| 14 Jul 2004 0:09 corner analysis of Vth |
|
|
|
|
| keep vdsat >100mV.
|
|
| Back to top |
|
|
naughtyboy
Joined: 18 Sep 2003
Posts: 13
|
| 14 Jul 2004 1:58 Re: corner analysis of Vth |
|
|
|
|
| Vth is also related to the channel DC bias. MOSIS only supports N-Well, so for a NMOSFET, the channel is always tired to ground. So the threshold voltage may be a lot higher than Vth0, when the source is not grounded.
|
|
| Back to top |
|
|
terryssw
Joined: 18 Apr 2004
Posts: 176
Helped: 14
|
| 14 Jul 2004 5:43 Re: corner analysis of Vth |
|
|
|
|
| How can you look on the value of Vdsat? by Vgs-Vth or by vdsat directly from DC operating point parameters? which one is more accurate? Also, how about the margin for Vds-Vdsat to keep it in satauration?
|
|
| Back to top |
|
|
naughtyboy
Joined: 18 Sep 2003
Posts: 13
|
| 14 Jul 2004 8:36 Re: corner analysis of Vth |
|
|
|
|
I use ADS2003, so you can get the device info my "detailed device ...". If you use HSpice, there is a commond to extract the DC parameters and put in the *.lis file.
Usually the input signal bias is not decided by the Vdsat of a current mirror underneath, but it does effect the output swing. For a large transistor, the Vdsat can be smaller than 0.1V, so not a big deal.
|
|
| Back to top |
|
|
