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Xilinx ise: How to map my fifo on LUT?
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fighter212



Joined: 30 May 2004
Posts: 6
Post07 Jun 2004 8:34   

lut_map constraint xst
I have designed an asynchronous fifo whose data width and depth are both 8. I used a lut_map constraint. But in related Xilinx document, it is said "Attaching a LUT_MAP constraint to this block will indicate to XST that this block must be mapped on a single LUT".
But obviously one lut is not enough for my fifo, what can I do if I want to use XST? My device family is Virtex2P.

Thanks!
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tlp71@hotmail.com



Joined: 14 May 2002
Posts: 476
Helped: 4
Post07 Jun 2004 9:08   

Re: Xilinx ise: How to map my fifo on LUT?
try if exist a xilinx library function where you can make a fifo using lut or ram.bye
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monnoliv



Joined: 09 Mar 2004
Posts: 104
Helped: 3
Location: Belgium
Post07 Jun 2004 13:24   

Re: Xilinx ise: How to map my fifo on LUT?
Hi,
With Altera qu(at)rtus II, I use megafunctions that have FIFO (one or two clocks) integrated, just drag'n drop on schematics. See if it exist with Xilink.
bye,
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