how to design a soc?

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atuo

Joined: 19 Feb 2004
Posts: 59
Helped: 1

20 May 2004 13:30 how to design a soc?

I want to study to design a soc , and where to find a soc design example?

open_cores?

eexuke

Joined: 25 Mar 2004
Posts: 200
Helped: 6

20 May 2004 15:43 Re: how to design a soc?

frankly speaking,compared with the traditional ASIC chip,SoC is a much much bigger design that contains several modules such as MCU, DSP, Video/audio codec..... on a single chip.I think opencores provides small chips (IPs) which maybe integrated in a Soc.

eltonjohn

Joined: 22 Feb 2002
Posts: 1751
Helped: 28

20 May 2004 16:26 Re: how to design a soc?

Check at www.Triscend.com . They were among the first companies to come up with a SoC chip and and a good developemnt tool

tom_hanks

Joined: 28 Aug 2003
Posts: 256
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20 May 2004 17:54 Re: how to design a soc?

for SOC..microcontroller is best example..
MC is SOC...u can say..

omara007

Joined: 06 Jan 2003
Posts: 1279
Helped: 39
Location: Dubai

20 May 2004 18:34 Re: how to design a soc?

SoC is a property of the system not a property of the system more than being a property of the design .. in other words, if the system u r designing is quite large and u want to put it on one chip then call it so .. this mandates u learn design hirarchy with such systems .. interconnects between component composing the system .. the steps of testing and verifing such systems and so on ..
P.S. SoC is something independant from the concept of ASIC and FPGA .. simply u can design the system on one chip and this chip can either be ASIC or FPGA .. specially nowadays highly densed FPGA chips.

Enjoy

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atuo

Joined: 19 Feb 2004
Posts: 59
Helped: 1

21 May 2004 8:20 Re: how to design a soc?

I want to know how to connect all IP cores in soc . Using AMBA or others ?
Why?

ram

Joined: 03 May 2004
Posts: 118
Helped: 4

21 May 2004 8:32 Re: how to design a soc?

YOu could use AMBA for connecting all the IP core. How ever there is a free core avliable on opencores which is wishbone, u can also go for that approch

zhangzhe

Joined: 13 Apr 2006
Posts: 2

13 Apr 2006 12:37 Re: how to design a soc?

atuo wrote:

I want to know how to connect all IP cores in soc . Using AMBA or others ?
Why?

AMBA is not free,you can also use wishbone or coreconnect

joe2moon

Joined: 19 Apr 2002
Posts: 389
Helped: 12
Location: MOON

13 Apr 2006 13:25 Re: how to design a soc?

http://www.edaboard.com/viewtopic.php?t=161132&highlight=
Title: 2 open source Processor
--------------------------------------------------------------------------------------------

1) [Verilog] -- Sun releases open-source processor @03/21/2006 (http://opensparc-t1.sunsource.net/nonav/source/verilog/html/verilog.html)

2) [VHDL] LEON2 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. (http://www.gaisler.com/products/leon2/leon.html)

vishwa

Joined: 11 Aug 2005
Posts: 156
Helped: 12
Location: India

13 Apr 2006 13:37 What is the difference between ASIC and SOC ?

What is the difference between ASIC and SOC ?

weng

Joined: 13 Jan 2006
Posts: 32

14 Apr 2006 2:35 Re: how to design a soc?

What is the difference between ASIC and FPGA?

salma ali bakr

Joined: 27 Jan 2006
Posts: 973
Helped: 80

14 Apr 2006 7:40 Re: how to design a soc?

so let me be clear on something here....a SOC is just some IPs on a circuit and has no relation with ASIC or FPGA
doesn't it need a prototype on FPGA first for some parts integration???
and is it converted to ASIC after all or it is just components on PCB ???
i am losing the concepts here....help me please

SkyHigh

Joined: 13 Jan 2005
Posts: 376
Helped: 51

14 Apr 2006 13:22 Re: how to design a soc?

weng and salma,

ASIC is a general word. Even Professor Michael Sebastian Smith (Hawaii) and Prof Jan Rabaey (Berkeley) claimed that the over-interchangable usage of terms confused designers themselves.

Here's the official definition of ASIC and FPGA.

ASIC = Application-Specific Integrated Circuits. It comes in two main families:
(1) Programmable ASICs such as FPGA, CPLD and SPLD.
(2) Custom ASIC - Full-Custom and Semi-Custom.

There is a 3rd family but not entirely classified as true ASIC is the standard components such as 7400s, 7420s, etc for simple logic gates. These are used in random logics for a specific application. For example, you may be designing a simple linear feedback shift register LFSR for pseudorandom generation of numbers using many D-Flip Flops and XOR gates, then such design and implementation is targetted as a SPECIFIC APPLICATION. Therefore it is also ASIC, but not a true ASIC.
Professor M. S. Smith also explained this in his books.

In practice, as a ASIC design engineer for over 5 years and a mixed-signal engineer for over 4 years, when we call ASIC, we usually mean the Semi and Full Custom ASIC. If we want to talk about programmable ASIC, we simply call FPGA, CPLD or etc. This is a conventional way of putting the word ASIC among ASIC designers.

Wherever you go, Europe, USA, Asia, the word ASIC usually refers to full or semi-custom ASIC. Not a doubt. Trust me!

It is usually the fresh graduates or poor graduates from lousy universities that didn't teach the right thing made them confused.

Note: ASIC does not necessary restrict itself to Digital. Even an A/D converter which is a mixed-signal component is considered a Full-Custom ASIC. This is because many A/D or D/A are manually done and tuned by the analog design engineer on Cadence Virtuoso/Spectre. Such "manual" work is considered Full Custom.
In the past, many microprocessors are done as full-custom IC or ASIC before the 90s when EDA-CAD tools were still quite primitive. Many engineers are employed to manual route cells and domains. This is not true today! Many microprocessors today are semi-custom because for ensuring functionality, only the working cores are re-used to speed TTM (time to market). It would be very silly to do full custom ASIC on digital today.

Here are the terms:
FPGA - Field Programmable Gate Array. It is a chip with a highly-organised array of SRAMs, MUXs, and Programmable Switch Matrices. The SRAMs are used as LUTs(Look-up Tables).
FPGA is used for rapid-prototyping using vendor tools such as Xilinx ISE and Altera Quatus II.
You may find FPGAs provided by Altera, Actel and Xilinx.
CPLD - Complex Programmable Logic Devices. It is a more complex version of SPLD.
SPLD - Simple Programmable Logic Devices such as Programmable Logic Arrays PLA (Programmable AND and OR Arrays), Programmable Array Logics PAL (Programmable AND, Fixed OR array), PROM (Programmable Read-Only Memory such as EEPROM or OTPROM etc). Examples of PAL is the AMD-Lattice 16v8 and 22v10 that have macrocells at the outputs, programmable AND array and fixed OR array.

SOC is System-on-Chip. It is about putting specific functional cores into a single chip solution. For example, putting MAXIM WLAN Transceiver core, Wolfson Codec core, MAXIM Power regulation core, Infineon 8k SRAM core, etc into a single chip.
SOC is not just putting only digital cores together. The concept also puts together RF, R-Analog/Mixed-Signal, Analog-baseband, Analog-Digital/Mixed-Signal Baseband, Digital baseband as well.
The greatest challenge in SOC is
(1) IP re-use issues and Patents
(2) Thermal and Hotspots
(3) High-frequency/EMI Issues
(4) High-speed Interconnect and Bus density Issues
(5) Very high mask costs to permit different technologies. For example, the digital and analog could be using 0.18 micron CMOS technology, but the RF might perform better in 0.25 micron or using SiGe instead. Therefore to compromise everything in a single CMOS technology is not easy at all.

You may have some digital cores previously and SUCCESSFULLY implemented in FPGA, then in ASIC, before re-using it into SOC.

SOC is not necessarily re-using components found in PCB. It is about putting SUCCESSFUL cores used in other ICs. Passives components used in PCB would instead be used as Embedded Passives under the substrate using a special surface mount technology unlike the ones used in SMT PCBs.