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nagraj
Joined: 17 Feb 2004
Posts: 52
Helped: 1
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 20 Mar 2004 8:54 clock data recovery....? |
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| how to take care clock data recovery in the design...any examples
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Google
AdSense
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20 Mar 2004 8:54 Ads |
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ucassbo
Joined: 23 Mar 2004
Posts: 5
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23 Mar 2004 13:21 Re: clock data recovery....? |
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| use a data-strobe technique to recover the clock with an XOR gate. see DS-DE for more info.
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zyphor
Joined: 22 Nov 2003
Posts: 100
Helped: 1
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24 Mar 2004 9:42 Re: clock data recovery....? |
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| some serdes design can be your reference.
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nagraj
Joined: 17 Feb 2004
Posts: 52
Helped: 1
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14 Jun 2004 17:30 Re: clock data recovery....? |
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well finally I found some solutions in xilinx application manuals of FPGA design on this topic...
If someone is interested they can read application manuals from the xilinx website under products and datasheets section.....
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layes2
Joined: 03 Dec 2004
Posts: 346
Helped: 5
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18 May 2005 8:21 Re: clock data recovery....? |
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what do you want
the lock time
the ber?
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justin.li
Joined: 08 Dec 2005
Posts: 14
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17 Jan 2006 0:14 clock data recovery....? |
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A SERDES receives a fast serial signal (e.g., 2.5 Gbits/s) and deserializes it into slower parallel signals (e.g., eight 311-Mbit/s signals). With data rates increasing, many companies want to integrate a SERDES into their ASICs and other large digital chips. Problems arise because IC suppliers aren't fully testing the SERDES before integrating it into a design. For ASIC customers, reducing costs requires the IC supplier to understand signal integrity issues, pre-test important intellectual property (IP), and provide testability features in the macros.
With the sharp, prolonged downturn in the communications industry, companies have shifted their focus from pursuing cutting-edge technology that builds network capacity to providing highly competitive offerings enabling new services at a much lower cost. Companies must leverage comprehensive communications IP portfolios and improve signal integrity. With the higher data rates, SERDES macrocell integration is one of today's most important issues. Integrating SERDES functions into larger, system-level ICs lowers system cost compared to standalone SERDES devices. Integration also cuts power consumption and improves signal integrity.
To win, companies must successfully integrate SERDES the first time, and pre-testing ensures that. Customers are demanding to see test silicon before integration and are increasingly sharing their frustration that SERDES providers are not enabling first-pass success. Keeping costs low begins with with first-pass success. It ends with ramping to production volume quickly.
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