| Author |
Message |
andy2000a
Joined: 18 Jul 2001
Posts: 756
Helped: 7
|
 26 Dec 2003 10:33 how to really reduce charge_injection in switch ?? |
|
|
|
Hi
Razavi book said , use dummy MOS can reduce charge_injection
and clock feed thru , but in hspice simulation , and real chip ASIC
sample/hold circuit , I can not find dummy MOS have wrok
why ??
|
|
| Back to top |
|
 |
mists
Joined: 14 May 2002
Posts: 380
Helped: 33
|
| 26 Dec 2003 12:58 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| maybe different input is a good choice
|
|
| Back to top |
|
|
andy2000a
Joined: 18 Jul 2001
Posts: 756
Helped: 7
|
| 26 Dec 2003 15:59 Re: how to really reduce charge_injection in switch ?? |
|
|
|
from Razavi Book said use differential is Good design .. I know it ,
but I problem is , if I use one path design , and text book said reduce by
dummy mos , hspice can not find it , the truth is "textbook"
or "hspice" , I think hspice maybe accuracy ..
have anyone know another method to reduce ( single path )
|
|
| Back to top |
|
|
Humungus
Joined: 10 Jul 2001
Posts: 417
Helped: 25
|
| 26 Dec 2003 23:25 Re: how to really reduce charge_injection in switch ?? |
|
|
|
A way to reduce charge injection is to put another switch that connects, assuming your input is on the top plate of the capacitor, the bottom plate of the capacitor to ground.
Once you have sampled your signal, first open the bottom plate switch. This would always produce the same ammount of charge injection. Then, when the main switch is opened, no extra charge injection will appear.
By doing so, charge injection only accounts as a fixed offset, which can be removed.
This method removes signal dependent charge injection, which in most cases is the most anoying component.
|
|
| Back to top |
|
|
rfsystem
Joined: 25 Feb 2002
Posts: 797
Helped: 85
|
| 29 Dec 2003 23:21 Re: how to really reduce charge_injection in switch ?? |
|
|
|
The charge injection is two effects.
1. CGDO or CGSO overlap cap.
That is a signal independed injection because the cap is linear. It could be compansated by a complementary driven MOS with half of the width and source and drain connected together to the cancelation node. The orientation should be equal.
2. Impedance dependence charge distribution.
The CGS and CGD channel cap injection has in most case equal charge distribution between sourse and drain. If the impedance is different the charge injection is also not 50%. So the balance does not work perfect. But I have seen rare circuits optimizing this effect.
|
|
| Back to top |
|
|
Hughes
Joined: 10 Jun 2003
Posts: 712
Helped: 84
|
| 04 Jan 2004 3:12 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| Use cmos trans gate may have a better result. But charge injection can not be cancelled completely.
|
|
| Back to top |
|
|
linxf2003
Joined: 19 Jul 2003
Posts: 33
|
| 12 Jan 2004 18:29 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| I have seen some designs using a shorted mos transistor with same type as the switch transistor to better match the charge.
|
|
| Back to top |
|
|
Hughes
Joined: 10 Jun 2003
Posts: 712
Helped: 84
|
| 13 Jan 2004 0:41 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| linxf2003 wrote: |
| I have seen some designs using a shorted mos transistor with same type as the switch transistor to better match the charge. |
I guess this method is what andy2000a proposed in the question -- dummy MOS.
|
|
| Back to top |
|
|
electronrancher
Joined: 24 Mar 2002
Posts: 474
Helped: 34
|
| 02 Feb 2004 9:07 |
|
|
|
looks like it.
rather than dummy mos, differential input is the only way i've seen to actually cancel out that burst of charge on a switching cycle. each input gets chopped by the same size transistor, so the chopper injection becomes common mode and is damped quite a bit by the PSRR of the amp
|
|
| Back to top |
|
|
hebu
Joined: 15 Nov 2004
Posts: 194
|
| 27 Jul 2005 12:29 Re: how to really reduce charge_injection in switch ?? |
|
|
|
But, I think the differential structure can improve the charge injection but
not exact. The signal depedent charge is depedent on the signal
level, definitely, the differential signals have different signal levels.
So, the charge injection level is also different.
|
|
| Back to top |
|
|
eda4you
Joined: 17 Sep 2002
Posts: 283
Helped: 17
|
| 27 Jul 2005 13:28 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| Reduce the rise and fall time of the clock!!!!
|
|
| Back to top |
|
|
Mline7
Joined: 28 Dec 2004
Posts: 34
Helped: 1
Location: Marseille, FRANCE
|
| 27 Jul 2005 16:38 Re: how to really reduce charge_injection in switch ?? |
|
|
|
Humungus and rfsystem have given you the right explanation concerning the ways to get rid of charge injection.
Concerning the differences between your hspice simulation and the theory, it simply comes from the fact that your transistor model simply don't account for chanel charge injection (the clock feedthrough, which is the coupling between switch gate and source through Cgs is sometimes included in charge injection, however it is easily modeled by the Cgs capacitor).
In fact, the chanel charge injection is very difficult to model. It depends on the input signal, on the gate slope, on the impedance seen from the source and from the drain. So, to simplify this, the usual transistor models simply feature a parameter (XPART for BSIM3v3) which value can be set to (as far as I remember):
- 0: 0% of chanel charge is transmitted to the source, and 100% to the drain
- 0.5: 50% of chanel charge is transmitted to the source, and 50% to the drain
- 1: 40% of chanel charge is transmitted to the source, and 60% to the drain
So, you've got to konw how your charge injection will be shared between source and drain (cf. rfsystem and Humungus), and then set the corresponding XPART value in you MOS model to correctly simulate your circuit.
|
|
| Back to top |
|
|
eda4you
Joined: 17 Sep 2002
Posts: 283
Helped: 17
|
| 28 Jul 2005 8:47 Re: how to really reduce charge_injection in switch ?? |
|
|
|
Hallo Mline71
The ratio (quote) of charge flowing to source or drain depends strongly on the rise and fall time. Simulation models are very worse. So you definitely cannopt trust the simulator. BTW if the rise/fall time is slow, the mos keeps longer during the switch off process in linear and than in saturation mode -> which results that most of the channel charge flows to the source and only less to the drain.
|
|
| Back to top |
|
|
Btrend
Joined: 26 Dec 2003
Posts: 423
Helped: 55
|
| 28 Jul 2005 12:15 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| Quote: |
| BTW if the rise/fall time is slow, the mos keeps longer during the switch off process in linear and than in saturation mode -> which results that most of the channel charge flows to the source and only less to the drain. |
As I know from text books, charge injection has two kind (maybe more ?):
1. Clock feedthrough : which is from CGSO, CGDO. and it occur only when the switch rising or falling. cause CGSO/CGDO form a high pass path from gate to S/D. and the noise is (VH-VL)*CGSO/(CGSO+Cs), where CS is the sampling cap.
during the clock high state, there is no more clock feedthrough noise.
and slow rise/fall time pulse (lower frequency) will be attenuated by the high pass filter (CGSO/CGDO). so noise will be smaller
2. Channel charge injection: which is from the channel charge formed previously when the swith is in ON state, u can imaing there is channel capacitor between source and drain. When the switch is OFF, these channel charge can not be absorbed to the substrate (chage conservation), so it will find a way (a low impedance path) to escape from the channel. the best way is the sampling cap.
so u will get a noise at Cs. but the rise/fall time has nothing to do with this channel charge, it depend on only ON or OFF state of the switch.
if I am wrong, correct me. thanks
|
|
| Back to top |
|
|
eda4you
Joined: 17 Sep 2002
Posts: 283
Helped: 17
|
| 28 Jul 2005 13:16 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| There is NO suddenly way to switch the transitor for on to off. Imagine the case the gate voltage decrease with the fall time. In case Vgate - Vth < Vd the Mos is in saturation. The channel is pinched-off. So more channel charge flows into the source as into the drain. A simple on-off modell don't explain how channel charge injection escapes.
|
|
| Back to top |
|
|
Btrend
Joined: 26 Dec 2003
Posts: 423
Helped: 55
|
| 29 Jul 2005 1:59 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| at the end of sampling , the VDS should be equal approximate to 0, such that u get the right input voltage(VS=VD). So, the SWITCH should be in triode region. After the end of ON, the Vgs decrease from VDD to 0, but the VDS is still low if the input signal (VD) do not cahnge abrupt.
|
|
| Back to top |
|
|
hebu
Joined: 15 Nov 2004
Posts: 194
|
| 29 Jul 2005 9:51 Re: how to really reduce charge_injection in switch ?? |
|
|
|
So, the conclusion is that it's diffcult to see the effect of charge injection in
simulation? but what's the glitch we can see in SC filter simulation?
who cause this phenomenon? And, how to know the performance of the means
used to overcome the charge injection?
|
|
| Back to top |
|
|
Btrend
Joined: 26 Dec 2003
Posts: 423
Helped: 55
|
| 29 Jul 2005 12:01 Re: how to really reduce charge_injection in switch ?? |
|
|
|
refer to the appendix1 in the following pdf
http://kabuki.eecs.berkeley.edu/~tcho/Thesis1.pdf
|
|
| Back to top |
|
|
hebu
Joined: 15 Nov 2004
Posts: 194
|
| 08 Aug 2005 7:05 Re: how to really reduce charge_injection in switch ?? |
|
|
|
I have one question on the dummy switch with inverse clock to solve charge
injection. Since the turned-on dummy can **** the charge of turned-off switch,
is it possible for the switch itself to **** the charge it left last phase?
|
|
| Back to top |
|
|
ocarnu
Joined: 05 Aug 2005
Posts: 91
Helped: 7
|
| 13 Aug 2005 21:40 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| No, becuase it sucks the charge from the lower impendance branch, i.e. the signal source. Anyway it doesn' matter, you hold phase was corrupted. The track phase is fine anyway.
|
|
| Back to top |
|
|
GDF
Joined: 11 Aug 2005
Posts: 175
Helped: 1
|
| 15 Aug 2005 16:45 Re: how to really reduce charge_injection in switch ?? |
|
|
|
1)So, no way can cancel the charge injection well up to now? is this a good
research topic?
2)Besides, we also see the charge injeciton effect in simulation, both in time
domain analysis and THD result. But the result is suspect?
3)How do I know how much charge injection is improved by simulation?
Or, the only thing I can do is just try all the methods and ignore the simulation?
|
|
| Back to top |
|
|
ocarnu
Joined: 05 Aug 2005
Posts: 91
Helped: 7
|
| 15 Aug 2005 18:13 Re: how to really reduce charge_injection in switch ?? |
|
|
|
1) there are more methods to either reduce it or transform it in a constant voltage (see clock boosted switches). Is not a good research topic becuase everything was done.
2,3) in simulation you cancel the charge injection completely, but this won't happen in a real circuit. You should extract with parasitics, run corners and you will get an idea.
|
|
| Back to top |
|
|
SkyHigh
Joined: 13 Jan 2005
Posts: 376
Helped: 51
|
| 15 Aug 2005 18:27 Re: how to really reduce charge_injection in switch ?? |
|
|
|
I think I was late to help.
One common method used by analog IC designers is to use advanced clocking at the shunt MOS. For details, refer to Ken Martin - Analog IC Design.
Another method is to transmission gates instead of NMOS. For details refer to Ken Martin - Analog IC Design.
Razavi's book is too theoretical and not deep enough. Perhaps in the US Razavi's book is commonly used. But Ken Martin's and Gray & Meyer, sometimes Allen's book, are much deeper and challenging for practising analog IC designers, for Asia and Europe. In Europe, Razavi's book doesn't sell well because it is not deep enough.
|
|
| Back to top |
|
|
ocarnu
Joined: 05 Aug 2005
Posts: 91
Helped: 7
|
| 15 Aug 2005 23:51 Re: how to really reduce charge_injection in switch ?? |
|
|
|
Come on, I read a lot of books on analog desing and Razavi's is one of the best. It does not cover everything, that is a undergrad book. Actually, Gray's better, but too detailed. Useless detail. Martin, for some reason I just don't like. Still, it is very usefull. But go ONLY with Martin to an interview and you will fail in no time.
Anyway, last time I checked on the "great" asian (even european) analog designers, they were working in Austin or San Jose. Tell me how many companies outside US use these amazing profound designers.
|
|
| Back to top |
|
|
tuza2000
Joined: 12 Nov 2004
Posts: 140
Helped: 5
|
| 16 Aug 2005 3:32 how to really reduce charge_injection in switch ?? |
|
|
|
how about the coms switch?
dummy transistor is a good choise,but sometimes the cmos switch is used more popular
|
|
| Back to top |
|
|
Freakwency
Joined: 26 Jan 2004
Posts: 7
|
| 16 Aug 2005 10:24 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| tuza2000 wrote: |
how about the coms switch?
dummy transistor is a good choise,but sometimes the cmos switch is used more popular |
The complementary switch may help, but the matching between the PMOS and NMOS is still another issue.
|
|
| Back to top |
|
|
GDF
Joined: 11 Aug 2005
Posts: 175
Helped: 1
|
| 22 Aug 2005 8:31 Re: how to really reduce charge_injection in switch ?? |
|
|
|
| Anybody has the idea how to check the effect of charge injection in simulation?
|
|
| Back to top |
|
|
mists
Joined: 14 May 2002
Posts: 380
Helped: 33
|
| 22 Aug 2005 10:30 how to really reduce charge_injection in switch ?? |
|
|
|
| i heared that the current spice model is not very accurate for charge injection simulation, but i am not sure.
|
|
| Back to top |
|
|
rfsystem
Joined: 25 Feb 2002
Posts: 797
Helped: 85
|
| 22 Aug 2005 11:20 Re: how to really reduce charge_injection in switch ?? |
|
|
|
This is my second reply:
I share the view that Razavi books provide less detail. He start presenting analog IC design with less math detail. That help to interest more people diving into analog. Earlier or later they have to get into detail of analog, which means math, otherwise they could not make dimension analysis or fail to predict and trade second order effects. That is needed in job. Hacking schematics and looking for waves is very ineffective. And you will block yourself getting more insight. So please do not stick with Razavi.
For SC circuits the charge-injection is an offset if it is not signal dependend. That offset could cancel up to mismatch if balanced circuit are used. The signal depend charge injection introduce nonlinear distortion. The second order component cancel up to mismatch by balanced circuits.
The injection could be reduced by dummy elements. The exact charge transfer is reasonable modelled in BSIM3V3 and up. If the model does not have S/D balanced model parameter setup for gate/drain and gate/source caps you can use two devices in schematic antiparallel. Extraction with an unbalanced model is not possible.
At the time of the switching the impedance of the source and the drain side have an effect on the charge distribution. But if SC circuits are used it does not matter where the charge is flowing after the channel is conducting. So more critical is the charge before conduction takes place. So you could analyses the charge effect before making connection and after. A constant, voltage independend gate/source or gate/drain cap works for the first analysis. Depending on control voltage and the potentials on both sides before conduction the 3 charges could be expressed.
So you could imagine that math is the base for an indeep analysis of a such a silly thing like charge injection.
If you try to avoid math you will fail.
|
|
| Back to top |
|
|
GDF
Joined: 11 Aug 2005
Posts: 175
Helped: 1
|
| 23 Aug 2005 13:52 Re: how to really reduce charge_injection in switch ?? |
|
|
|
I got a simulation result as attachment.
I fed a 2KHz sine wave to the SC low pass filter, whose 3dB frequency is 20KHz,
and the sampling rate is 900KHz. I got a wave form of the output of SCF, and use
dft function of the calculator in cadence. I got a result as attachment. We can
see the 3rd and 5th order harmonics in the plot. But, besides those harmonics of
fundamental, we also got the spurs at 30KHz, 34KHz, 62KHz and 66KHz...etc.
The voltage magnitude of fundamental frequency 2KHz is 620mV the 3rd and
5th are 0.26mV and 0.18mV.
1) Do I need to add other frequency components in addition to 3rd and 5th?
or just calculate 3rd and 5th? so the THD is around 66dB?
2) Anybody can explain why I got this result?
Thanks,
|
|
| Back to top |
|
|
