Joined: 10 Jan 2003 Posts: 29 Location: Russian Federation
26 Nov 2003 10:27 About Constraints and Attributes (Xilinx)
How it is possible to receive the set delay of a signal on output FPGA?
The project on Spartan. I use ISE4.1 + Synplify (VHDL).
Or how it is possible to use attribute "X" in VHDL? Whether is such constraints which forbid to delete logic at stage Map?
26 Nov 2003 12:34 Re: About Constraints and Attributes (Xilinx)
wasp wrote:
How it is possible to receive the set delay of a signal on output FPGA?
The project on Spartan. I use ISE4.1 + Synplify (VHDL).
Or how it is possible to use attribute "X" in VHDL? Whether is such constraints which forbid to delete logic at stage Map?
hi...as far as i understood ur question...tool always try to optimise the design...and reduce the timing...if u want to increase the delay..then u have to go to floorplan and place the logic away from the pin....
and ur second question i didn't follow it...attribute "X"..
and ur third question...to keep the logic without being deleted try the attribute "KEEP"....
