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Help: Implement design warnings (FPGA)

 
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avd



Joined: 05 Jul 2003
Posts: 12
Post07 Oct 2003 14:10   Help: Implement design warnings (FPGA)
Hi all,

Can anyone possibly help. When I run the 'Implement design' process in Xilinx ISE4,2i, I get 2 warnings. Can anyone tell me why? They are:

WARNING:Route:48 - The signal "VCC" has no driver so was not routed.

WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".

Thanks,
Andrew
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Al Farouk



Joined: 13 Jan 2003
Posts: 195
Post08 Oct 2003 9:22   Re: Help: Implement design warnings (FPGA)
for the first warning it seems that you had declar a signal called "VCC" and you did not assign logic '1' to it.
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cawan



Joined: 28 Dec 2002
Posts: 165
Helped: 7
Post10 Nov 2003 1:28   
be alert to your synthesis style.
par -xe is your extra effort level.
par -ol is your effort level.
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