CADDevil
Joined: 26 Jun 2001
Posts: 122
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 02 Oct 2003 21:13 AVR core from Opencores - syntax errors ? |
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Hello,
I am trying to simulate and synthetise the AVR core which I downloaded from www.opencores.org.
Anyone tried it ?
When I try to compile the IP for Modelsim (in FPGAdv 6.1), I am getting syntax errors.
But when I look at the sources, I can't see nothing wrong. Of course, my knowledge of VHDL is limited, but I checked it in the "Designer's Guide to VHDL") and everything seems OK.
Anyone can help ?
Thx CADDevil
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