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How to do post-synthesis simulation for A|ter@ FPGA??

 
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always@smart



Joined: 08 Feb 2002
Posts: 308
Helped: 7
Location: ASIA


Post02 Oct 2003 10:30   How to do post-synthesis simulation for A|ter@ FPGA??

Hi all,

Currently i'm doing an FPGA project,and might be using A|ter@ Cyclone FPGA family. I've just done some part of my design in the RTL code and verify it with ModelSim then synthesize it with Leornado Spectrum and qu(at)rtus II sperately.

First question of mine:
A. Now, How can I generate the netlist for the post-synthesis simulation for Modelsim??
B.How to generate it??
C.Where can I get the Cyclone's Technology file in Verilog Format??


Another further question:

A.How can I also do the post-layout simulation?? What files are required??
B. How to generate them??


Hope someone can answer my question ASAP...

Thank you so much

Regards,
Always(at)smart
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yev15



Joined: 22 Mar 2002
Posts: 49


Post02 Oct 2003 11:17   Re: How to do post-synthesis simulation for A|ter@ FPGA??

Then I made the Post Synthesis simulation for Acex, I used the output of Max+PlusII - an EDIF file.
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