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pandey.kapil@gmail.com
Joined: 08 Sep 2005
Posts: 1
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 08 Sep 2005 13:11 vera and specman LRM |
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Hi,
who go get the LRM of specman and vera?
Added after 13 minutes:
Hi
How i can learn specman,I realy want to learn this.
So kindly inform me how go get LRM or any document related to specman
Thanks
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Thomson
Joined: 15 Oct 2004
Posts: 181
Helped: 3
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09 Sep 2005 7:44 Re: SystemC , Systemverilog , vera , specman... |
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the following diagram basicly illustrates the SystemVerilog and other languages's development flow:
[img]
in addition, since SystemVerilog and SystemC are open languages and have many tool vendors to support them such that you're not restricted to only one tool vendor, which can bring you much flexibility and freedom.
in my opinion, proprietary languages such as e and openvera will doom to go to die.
currently many tool vendors such as Mentor and synopsys and other vendors has supported all or many of the features provided by Systemverilog. and SystemC is widely supported among the eda tool vendors, which is fundamentally a modeling language which leverage your modeling efficiency.
all the materials about SystemVErilog can be searched in the web of www.accellera.com, SystemVerilog is presided by this organization.[/img]
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brianhe
Joined: 04 Jul 2002
Posts: 20
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10 Sep 2005 10:05 Re: SystemC , Systemverilog , vera , specman... |
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Specman is great but also expensive.
System verilog is well defined but sill not mature and well supported
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sansprint
Joined: 01 Sep 2005
Posts: 22
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13 Sep 2005 2:23 Re: SystemC , Systemverilog , vera , specman... |
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| you can go to synopsys'free download,there is lrm
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ldm
Joined: 14 Oct 2005
Posts: 39
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04 Nov 2005 17:22 Re: SystemC , Systemverilog , vera , specman... |
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| sansprint, where can I download OpenVera or SystemVerilog?
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hayang
Joined: 17 Dec 2003
Posts: 11
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16 Nov 2005 4:08 SystemC , Systemverilog , vera , specman... |
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| i don't know why someone said "systemVerilog is slow", from general understanding, using any third party EDA tool will make the simulator slow. But if we use systemVerilog we don't need any third-party tool through PLI interface. so, using systemVerilog is faster. is my understanding correct?
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asilic
Joined: 19 Jan 2005
Posts: 1
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16 Nov 2005 18:01 SystemC , Systemverilog , vera , specman... |
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| in my company,now using E ,vera and systemC ,but not systemverilog,is there any tools support systemverilog now?
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vikadik
Joined: 03 Dec 2004
Posts: 61
Helped: 4
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30 Oct 2009 22:08 Re: SystemC , Systemverilog , vera , specman... |
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| All major companies like cadence ( SOC encounter ), Magma have updated there tools for using SV.
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ljxpjpjljx
Joined: 05 May 2008
Posts: 533
Helped: 12
Location: Shang Hai
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31 Oct 2009 4:35 Re: SystemC , Systemverilog , vera , specman... |
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now SV is very popular for verification and design !
SystemC can be very useful for agrithem modeling!
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pini_1
Joined: 18 Jun 2007
Posts: 288
Helped: 17
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31 Oct 2009 7:21 Re: SystemC , Systemverilog , vera , specman... |
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"For me system C is a great, license-free and high performance hardware simulator with the C++ as a verification engine....."
http://bknpk.no-ip.biz/my_web/First_SCV/aisTB.html
Many other examples in the site.
The site also inclusdes some specman examples:
"....The entire package can be downloaded from: specman performance test code
It includes the VERILOG test-bench, specman e-code, script to compile and run + specman profiler results. The design was used on NCSIM simulator...."
http://bknpk.no-ip.biz/my_web/specman_performane/specman_performane_1.html
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