SystemC , Systemverilog , vera , specman...

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amarnath

Joined: 24 Apr 2003
Posts: 939
Helped: 18

27 Feb 2004 18:59

i think ultimately system c will win the race...

blacklancer

Joined: 07 Nov 2003
Posts: 7

09 Mar 2004 16:19 Re: SystemC , Systemverilog , vera , specman...

I think systemverilog is better,but it need some days to popularize.
specman need support of EDA tool vendor.

Bajaj

Joined: 19 Aug 2001
Posts: 31

09 Mar 2004 19:49 Re: SystemC , Systemverilog , vera , specman...

combination of system c and system verilog

bagane

Joined: 12 Mar 2004
Posts: 7

12 Mar 2004 7:04

I think SystemC is better

lemon

Joined: 11 Mar 2004
Posts: 2

12 Mar 2004 14:59

I also prefer to system verilog

bbtjacking

Joined: 23 Feb 2004
Posts: 27

13 Mar 2004 6:11

As well as I know,SystemC is best for system level and RTL verificaion. And some company, such as Cadence and Synopsys will be focus on this field. For instance, in order to make systemc better for verification, Cadence extend the systemc into CVE according to join some Randomization and concurrency verification methodology and functions into systemc library.

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u571

Joined: 14 Mar 2004
Posts: 0

14 Mar 2004 16:29

I think systemC is better, for good interface with C++/C.

omara007

Joined: 06 Jan 2003
Posts: 1283
Helped: 39
Location: Dubai

07 Apr 2004 20:24 Re: SystemC , Systemverilog , vera , specman...

anyone can direct me to where i can download any e-book for systemC ?

I have heard that there is a good one called (System Design with SystemC) .. is it available here on servers ? .. or even anywhere on the internet ?

ramesh

Joined: 19 Jan 2003
Posts: 1260
Helped: 5

13 Jun 2004 16:39 Re: SystemC , Systemverilog , vera , specman...

edacw wrote:

SystemVerilog is very good!

Please give reasons whenever you say "it is very good" when compared with others. Otherwise the post may be classified as "useless post" by Moderators!

reddy

Joined: 22 Jun 2004
Posts: 19
Location: Bangalore, India

22 Jun 2004 5:25 SystemC , Systemverilog , vera , specman...

VERA is Better in my opinion. Because, it is having all the OOP features. Moreover I did not use others.
So, no comment on other lang.

foster_cn

Joined: 14 Jan 2003
Posts: 74
Helped: 2

23 Jun 2004 7:08 SystemC , Systemverilog , vera , specman...

Any of them, depends on the projects

zwj_seu

Joined: 12 Jun 2004
Posts: 43

25 Jun 2004 4:45 SystemC , Systemverilog , vera , specman...

I'm using specman now.It maybe hard to learn at the beginning,but it's powerful !

zhangpengyu

Joined: 28 Jun 2004
Posts: 177
Helped: 2

28 Jun 2004 12:24 SystemC , Systemverilog , vera , specman...

Specman is best!

ram

Joined: 03 May 2004
Posts: 118
Helped: 4

16 Jul 2004 10:42 Re: SystemC , Systemverilog , vera , specman...

Now a days many companies are prefering systemc over e....
The reason is simple...the clint which they are going to suplly may not have specman licence...and systemc is free

yerics

Joined: 25 Sep 2003
Posts: 40
Location: Beijing，China

26 Jul 2004 8:24 Re: SystemC , Systemverilog , vera , specman...

Just as ram said , specman is too expensive , but it is a very great tool.
our boss decide to not purchase specman license any longer next year.

HHH
we will have to use other ...to do verification work
may be systemC

ram wrote:

Now a days many companies are prefering systemc over e....
The reason is simple...the clint which they are going to suplly may not have specman licence...and systemc is free

mami_hacky

Joined: 28 Mar 2002
Posts: 724
Helped: 4
Location: Some where

01 Aug 2004 17:05 SystemC , Systemverilog , vera , specman...

Umm, I studied all of the messages here. the result, I think is to use SystemC and SystemVerilog. and to leave e, and vera. Yes?

SystemC is now supported by both of synopsys and cadence, however, no other languge here has such a propery.

correct?

seasonyangd

Joined: 14 Nov 2001
Posts: 80

02 Aug 2004 4:34 SystemC , Systemverilog , vera , specman...

If you have experience with c/c++ programming. I suggest you SystemC. You can use it fluently. Cadence Incisive had integerated teh GDB into their debug env (I have not test it). Also, you can use TXE to analyse the data base and do function coverage analysis.

sansprint

Joined: 01 Sep 2005
Posts: 22

01 Sep 2005 10:02 hello ,can i ask you some question about openvera?

hi,Can you tell me something about it ?I had studied it for a month,but i really don't know how to write a programe,can you tell how to write ?Thank you very much! Very Happy

omara007

Joined: 06 Jan 2003
Posts: 1283
Helped: 39
Location: Dubai

01 Sep 2005 10:44 Re: hello ,can i ask you some question about openvera?

sansprint wrote:

hi,Can you tell me something about it ?I had studied it for a month,but i really don't know how to write a programe,can you tell how to write ?Thank you very much! Very Happy

try a simple program .. chose a very simple one .. like a module with one input port and one output port .. chosen any style in the literature for coding .. and make one process .. let it be sc_method for example .. and in the cpp file write one statement .. cout << " Hi" ..

then if it works .. try to append something .. make some cin's .. try some if condition statements ... then upgrade urself to sc_thread .. try waits ..

u can also go to www.systemc.org and just listen to the discussions ..

rakeshnunna

Joined: 19 Apr 2005
Posts: 80
Helped: 6

01 Sep 2005 15:59 Re: SystemC , Systemverilog , vera , specman...

In my opinion System Verilog is the most promising

nanako

Joined: 20 Jul 2001
Posts: 119

01 Sep 2005 16:04 Re: SystemC , Systemverilog , vera , specman...

systemverilog does look promising as if you look at the LRM, basically it could do almost everything under the sun but the current support by the EDA vendor on their simulator with systemverilog is still far from what the standard is capable of doing.

jjww110

Joined: 19 Apr 2005
Posts: 262
Helped: 5
Location: china

02 Sep 2005 10:27 SystemC , Systemverilog , vera , specman...

systemverilog will win in the future!!

sansprint

Joined: 01 Sep 2005
Posts: 22

02 Sep 2005 14:46 Re: SystemC , Systemverilog , vera , specman...

omara007,thank you for you tell me so much !Because my english is so bad ,so i don't konw how to express my question,i'm so sorry!:|but can anyone give me an example: a verifiction program write by openvera?a very simple one .thank you very much !

cnspy

Joined: 10 Sep 2002
Posts: 155
Helped: 3

06 Sep 2005 8:26 SystemC , Systemverilog , vera , specman...

Cadence does not support systemverilog very well. I am testing the assertion of SV. But ncsim does not support such as: not and clock edge between sequence .

dqsh06

Joined: 02 Apr 2005
Posts: 3
Location: Tokyo, Japan

06 Sep 2005 8:52 SystemC , Systemverilog , vera , specman...

It is a very old topic, i think. now Cadence has perchased verisity. so E language (specman) can be a good choice for verification. Systemc is not a verification language, it is for system modeling.
Vera, PSL　are all verification language.

zcg

Joined: 19 May 2004
Posts: 19

06 Sep 2005 10:37 Re: SystemC , Systemverilog , vera , specman...

old_cat wrote:

I think specman 'e' is good!

First, it's a mature verification language and excellent support from verisity. Maybe, verisity is only a little-boy so they have to do good support.

Second, it's a aspect-oriented language, easy to use and you can extend new funcionalities easily.

Anyway, who likes to be verification engineer? It's hard to find a job as a verification engineer in the north american. It is better to be ASIC designer rather than verification engineer.

Shocked

First ,specman E is good but not generally supported by other EDA company. System C and system verilog maybe have more bright future to be common standard.

Second, I think you have a wrong idea of verification job. In fact a good verification engineer should have more knowledge than RTL engineer. Many of them are tranfered from skilled design engineers.