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roadrunner
Joined: 31 Oct 2001
Posts: 31
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 28 Sep 2003 7:37 history of verisity specman |
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Hi All : For those languages which is suitable for verifatin engineer need
to know! Do't tell me all of them , This wil kill me!
Any commend!
rgds roandrunner
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28 Sep 2003 7:37 Ads |
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lovelyic
Joined: 28 Apr 2002
Posts: 52
Helped: 1
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| 28 Sep 2003 8:27 |
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i think e-language(specman) is suitable!
but now i use vera. 
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linuxluo
Joined: 26 Jul 2002
Posts: 516
Helped: 4
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28 Sep 2003 10:46 Re: SystemC , Systemverilog , vera , specman... |
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hi,
I think vera,coz ova is very simple to use . and you can use vera to establish your own testbench quickly and easily.
and who can tell me the advantage of specman?
I just heard it and never use it.
thanks.
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rx300
Joined: 02 Mar 2002
Posts: 61
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30 Sep 2003 4:43 Re: SystemC , Systemverilog , vera , specman... |
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SystemVerilog looks attractive. However, it's still some distance away from being accepted by IEEE. Plus, except for VCS from Synopsys, who else supports SystemVerilog?
Vera is being phased out since Synopsys is promoting SystemVerilog now. The Vera code written today might become completely useless in a few years. Same with Specman. If the company dies in a few years, all the eVCs developed today will be useless. Currently there is no sign that any of the large EDA houses is interested in acquiring Verisity, the maker of Specman. So there is some uncertainty regarding this tool. However, the current customer base for Specman is probably the largest among all 4 tools.
SCV looks very attractive. I haven't had enough time to look into it yet. I'd like to seem someone comment on that one.
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Joyee
Joined: 26 May 2001
Posts: 26
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30 Sep 2003 6:11 Re: SystemC , Systemverilog , vera , specman... |
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I just think E can survive in the future years since IEEE appears to be very headache about systemverilog and does not want to accept it as a new verilog standard. For systemverilog, cadence also doesn't plan to support such a mixed language(design and verification, two quite different tasks). Therefore, just synopsys is planning to support its own language, however, it looks so hard so far.
Additionally, VERA has been out of date since no vendor wants to support it. But, the situation of Language E is quite different from that of VERA. Verisity supports this language and IEEE has accept it as a preliminary standard for verification language. Besides this, a lot of companies, say IBM, Cadence and Intel are also on the side of Verisity.
It's said, in 1998, Synopsys wanted to acquire Verisity, but, "unfortunately" (for synopsys), Verisity didn't want to sell it.
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galant
Joined: 19 Jun 2003
Posts: 58
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07 Oct 2003 9:06 Re: SystemC , Systemverilog , vera , specman... |
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| As well as I know,SystemC is best for system level and RTL verificaion. And some company, such as Cadence and Synopsys will be focus on this field. For instance, in order to make systemc better for verification, Cadence extend the systemc into CVE according to join some Randomization and concurrency verification methodology and functions into systemc library.
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aramis
Joined: 07 Apr 2002
Posts: 103
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07 Oct 2003 9:31 Re: SystemC , Systemverilog , vera , specman... |
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If i'm wrong, please correct me.
I think systemC will not be as important as before, cuase synopsys will start to push their systemverilog, Cadence used to not support systemC in their flow. but when systemverilog is out, cadence start to push SystemC with their verification library.
In many synopsys product, they already have VERA support(eg. VIP)
so i think in this language battle, sysnopsys is now win cadence.
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joe2moon
Joined: 19 Apr 2002
Posts: 389
Helped: 12
Location: MOON
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07 Oct 2003 13:16 Jeda |
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A potential alternative to the testbench extensions in SystemVerilog 3.1...
----------------------------------------------------------------------------------
"The SystemVerilog 3.1 verification layer came from Vera,
which originated from lots of my ideas," said Atsushi Kasuya,
Jeda Technologies' chief technology officer and
the author of two Vera patents.
----------------------------------------------------------------------------------
The technology that Jeda has donated to the IEEE 1364 Verilog committee
includes object-oriented programming support for
* writing testbenches,
* aspect-oriented programming support,
* enhanced list and array data types for behavioral modeling,
* concurrent programming support,
* various synchronization primitives for multithreaded execution and
* cycle-based testbench support.
----------------------------------------------------------------------------------
ref: http://www.eedesign.com/story/OEG20031006S0065
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yorkiny
Joined: 12 Aug 2002
Posts: 25
Location: CHINA
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| 13 Oct 2003 11:17 |
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yes, Jeda verifivation tool is faster than all of them and easy to learn like Vera, but its Gui interface is very simple.
An article about Jeda and IEEE standard:
http://www.eedesign.com/news/OEG20031006S0065
Press Release:
http://biz.yahoo.com/bw/031006/65015_1.html
Jeda Tutorial:
http://www.eedesign.com/features/exclusive/OEG20031001S0036
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old_cat
Joined: 04 Mar 2002
Posts: 17
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27 Oct 2003 21:25 Re: SystemC , Systemverilog , vera , specman... |
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I think specman 'e' is good!
First, it's a mature verification language and excellent support from verisity. Maybe, verisity is only a little-boy so they have to do good support.
Second, it's a aspect-oriented language, easy to use and you can extend new funcionalities easily.
Anyway, who likes to be verification engineer? It's hard to find a job as a verification engineer in the north american. It is better to be ASIC designer rather than verification engineer.
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crystal
Joined: 12 Jun 2003
Posts: 131
Helped: 3
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| 29 Oct 2003 6:47 |
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One point which you have to consider - Vera or OpenVera is a standard open language which any one can learn & use it, where else, 'e' is a proprietary language by Verisity.
Synopsys claimed that Vera has a roadmap/path towards SystemVerilog but Verisity doesn't.
What do you think of that?
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rx300
Joined: 02 Mar 2002
Posts: 61
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06 Nov 2003 5:24 Re: SystemC , Systemverilog , vera , specman... |
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| old_cat wrote: |
I think specman 'e' is good!
Anyway, who likes to be verification engineer? It's hard to find a job as a verification engineer in the north american. It is better to be ASIC designer rather than verification engineer.
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That's not right. I see more openings for verficiation engineers than RTL designers. The barrier for RTL design is much lower now. However, to become a good verification engineer, it takes quite some effort. Specman is not easy to learn and master.
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thecat
Joined: 04 Feb 2002
Posts: 37
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10 Nov 2003 16:39 Re: SystemC , Systemverilog , vera , specman... |
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I also prefer to do design ... but I'm doing verification in Specman.
I could anytime switch on doing design, while a design engineer will require a period of accomodation with the verification tools/languages in order to do a good verification job.
As I saied in other post:
Specman it's used especially for it's lists and coverage features. If Verilog for example would have the possibility of generating dinamic structures (lists) and collecting functional coverage, Specman wouldn't have appeared.
In fact I think that the usage of specman will decrease ater the release of ModelSim 5.8 which will have full supoport for SystemC language that has all the features of the E language.
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linuxluo
Joined: 26 Jul 2002
Posts: 516
Helped: 4
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11 Nov 2003 1:33 Re: SystemC , Systemverilog , vera , specman... |
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hi, all
If I make mistake, pls correct me.
I just use vera from synopsys. And I think it's simple to master and use.
Can anyone tell me something about specman .
And I think systemverilog is also simple. So can I draw a conclusion that systemverilog will be popular?
thanks for any comments.
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thecat
Joined: 04 Feb 2002
Posts: 37
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11 Nov 2003 9:00 Re: SystemC , Systemverilog , vera , specman... |
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I took a look on the SystemVerilog LRM and I didn't see any coverage like constructs.
If SystemVerilog will support the functional coverage, it will be my favourite too.
The SystemC Verification Library (SCV) seems to have a transaction collecting system (coverage like) but I didn't try it. I wait the release of ModelSim 5.8 which will support SystemC.
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BlueSky68
Joined: 10 Nov 2003
Posts: 28
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12 Nov 2003 20:41 Re: SystemC , Systemverilog , vera , specman... |
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I personally belive that SystemVerilog will finally take all the other languages and third party 'E' languages our of the scene.
It has all the power for the ASIC design and verification. I just attended
SystemVerilog Now seminar across North America. It was very good and I strongly recommend those who are interested to take it.
Regards,
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rx300
Joined: 02 Mar 2002
Posts: 61
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13 Nov 2003 2:01 Re: SystemC , Systemverilog , vera , specman... |
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| I've browsed through the SystemVerilog training slides. It looked impressive on paper. However, the future of SystemVerilog is still not clear. First, it's not accepted by IEEE yet. And it won't become a standard before 2005. Second, how many other EDA vendors support SystemVerilog?
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andromeda
Joined: 26 Sep 2002
Posts: 71
Helped: 1
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05 Jan 2004 5:45 Re: SystemC , Systemverilog , vera , specman... |
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Purpose of SystemC is different then purpose of OpenVera or e, and this language will be used in parallel with SystemVerilog (if Synopsys win).
I don't think that there is future for e. This language and tool (Specman) are the most powerful on the market, but very complicated to learn. It is true that Specman covers 70% of this market those days and that e is IEEE standard now, but Synopsys is very good in dirty wars and I think this will prevail.
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DeepIC
Joined: 13 Oct 2001
Posts: 60
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| 07 Jan 2004 15:00 |
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| did E become IEEE standrad?
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maniasonic
Joined: 08 Jan 2004
Posts: 35
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| 08 Jan 2004 11:22 |
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| c(at)dence has announced to support SystemVerilog. thus SystemVerilog become the most promising language for verification, I think. Although e-language may be much better.
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jasonxie
Joined: 28 Dec 2001
Posts: 12
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| 09 Jan 2004 20:04 |
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| Based on what I know, Vera would be fully integrated into VCS since Version 7.2 (Q2/04), which means free of license fee. So my boss would not like to change from Vera to E.
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weilijun
Joined: 20 Jan 2004
Posts: 30
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20 Jan 2004 6:49 Re: SystemC , Systemverilog , vera , specman... |
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Vera is easy to learn and use.
In the future, if the main simulator can support SystemVerilog3.1, SystemVerilog is sure to play an important part in the verification field.
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harrysoin
Joined: 14 Jan 2004
Posts: 31
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| 10 Feb 2004 10:35 |
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| i don't think vera in the future ,
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semicon
Joined: 18 Feb 2004
Posts: 12
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18 Feb 2004 7:17 Re: SystemC , Systemverilog , vera , specman... |
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i use systemc in SoC system design now.
it's perfect.
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foster_cn
Joined: 14 Jan 2003
Posts: 74
Helped: 2
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18 Feb 2004 9:23 Re: SystemC , Systemverilog , vera , specman... |
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systemc is for system modelling
vera, specman is for verification
systemverilog is trying to do both.
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satya
Joined: 14 Jun 2001
Posts: 85
Helped: 2
Location: bangalore
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20 Feb 2004 5:25 Re: SystemC , Systemverilog , vera , specman... |
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Hi,
I just dont understand why these language battles among EDA majors..??
as I see, specman 'e', vera,systemverilog and PSLs( mostly Intel and IBM use) all for verification support. But as for my knowledge, PSLs are very powerful for verification (correct me if i m wrong) coz you can specify certain properties in very simple and in one-liners.
I donno why synopsys is digging it's own pit?? if it pushes forward systermverilog, it loses whatever it has with its vera now )
- satya
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zyphor
Joined: 22 Nov 2003
Posts: 100
Helped: 1
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20 Feb 2004 7:12 Re: SystemC , Systemverilog , vera , specman... |
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system c will dying
and
vera has no support
specman is too expensive
So we are waiting systemverilog
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beta0
Joined: 24 Nov 2003
Posts: 120
Helped: 7
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| 23 Feb 2004 13:53 |
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In our company ,we use systemc for system level
design and verification , it's work so good and make
hardware engineer and software engineer understanding eachother more effictively!
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radix
Joined: 23 Jul 2002
Posts: 157
Helped: 5
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24 Feb 2004 19:21 Re: SystemC , Systemverilog , vera , specman... |
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Check out:
http://www.reed-electronics.com/ednmag/article/CA376625?text=systemc&stt=000
It's an article from the 2/5/04 issue of EDN entitled "The search for the perfect language". Good history and overview of the various HDLs. Click on the link for Table1 to get a PDF with a decent side-by-side comparison of some of the features of the different languages.
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edacw
Joined: 29 Sep 2002
Posts: 16
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| 27 Feb 2004 17:25 |
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| SystemVerilog is very good!
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