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Tomby
Joined: 29 Aug 2003
Posts: 22
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 25 Sep 2003 3:56 xilinx bit files |
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| Can anyone tell me whether the bit files ise generates for the different modes(i.e. master/slave serial etc. and jtag) is always the same? If it is the same then only the mode pins tell what mode is actually to be used to program the fpga? What if jtag is avaible for all the mode selections such as in spartan xcs chips? Thanks
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zcq
Joined: 14 Jul 2001
Posts: 112
Helped: 1
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| 25 Sep 2003 16:08 |
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I dont think they are the same. Just guess!
Hope anybody can confirm it!
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ktuluboy
Joined: 27 Sep 2002
Posts: 4
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| 25 Sep 2003 18:29 Re: xilinx bit files |
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I know for sure that if you connect a JTAG port and try to download a BIT file with it, it will override any of the programming mode selected by the mode pin.
For the difference between the two BIT files....There's a difference between the two of them...and I think it's only one bit in the BIT file (but i'm not so sure about that).
Ktuluboy
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ktuluboy
Joined: 27 Sep 2002
Posts: 4
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| 25 Sep 2003 18:32 |
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Oh yeah... I don't remember with Xilinx ISE 4.2...but i know that witht XIlinx ISE 5.1, when you try to program a bit file via JTAG that has been generated to start with the CCLK set as it's starting clock, the software will warn you about it (and i think it ask you to modify the bit file to use the proper starting clock).
ktuluboy
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tlp71@hotmail.com
Joined: 14 May 2002
Posts: 451
Helped: 3
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| 25 Sep 2003 18:34 Re: xilinx bit files |
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The only difference is for the device or for the architecture, ex prom serial or parallel.
Bye.
G.
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Ohh2
Joined: 30 May 2003
Posts: 13
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| 26 Sep 2003 9:59 Re: xilinx bit files |
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| For the same design you may have different configuration commands (incl. parameters) in the bitstream. For example, you can specify either using Jtag clock or CCLK.
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