need help on coreconnect plb slave ip interface design

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Raptor

Joined: 06 Jul 2001
Posts: 50
Helped: 2

20 Sep 2003 13:06 need help on coreconnect plb slave ip interface design

hi all,

i'm doing a project on plb(processor local bus) slave ip interface.i need some help on the following

1.PLB bus has a compress signal i could not find what type of compression algorithm is used.

2.what does well behaved memory means.its comes in guarded access of plb bus.

3.if slave databus is of 64bit and master is requesting a write of only one byte how it is achieved because other bytes in the word may be overwritten.

if some can also tell me what should be the standard signals for ram and fifo which goes from slave ip interface to ram and fifo.

any reference internal architecture would be of great help.

thanx in advance
take care and bye